Revision 1.01 – September 21, 2005
S5920 – PCI Product
Data Book
Figure 1. AMCC Product Development Strategy ................................................................................................... 14
Figure 2. S5920 Block Diagram ............................................................................................................................. 27
Figure 3. S5920 Pinout .......................................................................................................................................... 29
Figure 4. Mailbox Block Diagram ........................................................................................................................... 30
Figure 5. Pass-Thru Block Diagram ....................................................................................................................... 31
Figure 6. S5920 Pin Assignment ........................................................................................................................... 33
Figure 7. Vendor Identification Register ................................................................................................................. 42
Figure 8. Device Identification Register ................................................................................................................. 43
Figure 9. PCI Command Register .......................................................................................................................... 44
Figure 10. PCI Status Register .............................................................................................................................. 46
Figure 11. Revision Identification Register ............................................................................................................ 48
Figure 12. Class Code Register ............................................................................................................................. 49
Figure 13. Cache Line Size Register ..................................................................................................................... 54
Figure 14. Latency Timer Register ......................................................................................................................... 55
Figure 15. Header Type Register ........................................................................................................................... 56
Figure 16. Built-In Self-Test Register ..................................................................................................................... 57
Figure 17. Base Address Register - Memory ......................................................................................................... 59
Figure 18. Base Address Register - I/O ................................................................................................................. 60
Figure 19. Subsystem Vendor Identification Register ............................................................................................ 63
Figure 20. Subsystem Identification Register ........................................................................................................ 64
Figure 21. Expansion ROM Base Address Register .............................................................................................. 65
Figure 22. Interrupt Line Register .......................................................................................................................... 67
Figure 23. Interrupt Pin Register ............................................................................................................................ 68
Figure 24. Minimum Grant Register ....................................................................................................................... 69
Figure 25. Maximum Latency Register .................................................................................................................. 70
Figure 26. Outgoing Mailbox .................................................................................................................................. 72
Figure 27. Incoming Mailbox .................................................................................................................................. 73
Figure 28. Mailbox Empty/Full Status Register (MBEF) ......................................................................................... 74
Figure 29. Interrupt Control Status Register .......................................................................................................... 75
Figure 30. FIFO Control/Status Register ............................................................................................................... 77
Figure 31. Pass-Thru Configuration Register ........................................................................................................ 79
Figure 32. Mailbox Empty/Full Status Register ...................................................................................................... 83
Figure 33. Add-On Interrupt Control Status Register ............................................................................................. 85
Figure 34. Add-On General Control/Status Register ............................................................................................. 87
Figure 35. Pass-Thru Configuration Register ........................................................................................................ 89
Figure 36. S5920 to nvRAM Interface .................................................................................................................... 93
Figure 37. Serial Interface Definition of Start and Stop .......................................................................................... 93
Figure 38. Serial Interface Clock Data Relationship .............................................................................................. 93
Figure 39. Serial Interface Byte Access-Write ....................................................................................................... 94
Figure 40. Serial Interface Byte Access-Read ....................................................................................................... 94
Figure 41. Serial Byte Access- Sequential Read ................................................................................................... 94
AMCC Confidential and Proprietary
DS1596
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
