Revision 1.01 – September 21, 2005
S5920 – PCI Product
Data Book
Figure 42. PCI AD Bus Definition Type 0 Configuration Access ............................................................................ 98
Figure 43. Type 0 Configuration Read Cycles ....................................................................................................... 98
Figure 44. Type 0 Configuration Write Cycles ....................................................................................................... 99
Figure 45. Single Data Phase PCI Bus Read of S5920 Registers or Expansion ROM ....................................... 104
Figure 46. Burst PCI Bus Read Attempt to S5920 Registers or Expansion ROM ............................................... 104
Figure 47. Burst PCI Bus Write of S5920 Registers ............................................................................................ 105
Figure 48. Figure 4a. Target Disconnect Example 1 ........................................................................................... 105
Figure 49. Figure 4b. Target Disconnect Example 2 ........................................................................................... 105
Figure 50. Figure 5. Target-Initiated Retry ........................................................................................................... 106
Figure 51. Figure 6. Engaging the LOCK# Signal ................................................................................................ 106
Figure 52. Access to a Locked Target by its Owner ............................................................................................ 109
Figure 53. Access Attempt to a Locked Target .................................................................................................... 109
Figure 54. Error Reporting Signal ........................................................................................................................ 109
Figure 55. Figure 1. PCI to Add-On Mailbox Register .......................................................................................... 110
Figure 56. Add-On to PCI Mailbox Register ......................................................................................................... 111
Figure 57. Input/Output Mode (MDMODE=0) ...................................................................................................... 113
Figure 58. Input Mode (MDMODE=1) .................................................................................................................. 113
Figure 59. Read Operation Register .................................................................................................................... 119
Figure 60. Write Operation Register .................................................................................................................... 119
Figure 61. 16 Bit Mode Operation Register DWORD Write/Read ........................................................................ 120
Figure 62. PCI To Add-On Passive Write ............................................................................................................ 126
Figure 63. PCI To Add-On Passive Write w/Pass-Thru Address ......................................................................... 126
Figure 64. PCI To Add-On Passive Read ............................................................................................................ 127
Figure 65. PCI to Add-On Passive Burst Write .................................................................................................... 128
Figure 66. PCI to Add-On Passive Burst Write Using PTRDY# to assert Wait-States ........................................ 130
Figure 67. PCI to Add-On Passive Burst Read Access ....................................................................................... 130
Figure 68. PCI to Add-On Passive Burst Read .................................................................................................... 132
Figure 69. PCI to Add-On Passive Write to an 8-bit ............................................................................................ 136
Figure 70. PCI to Add-On Passive Read to an 16-bit Add-On Device ................................................................. 138
Figure 71. Active mode PCI Read (Zero Programmed Wait States) with PTADR# ............................................. 139
Figure 72. Active Mode PCI Read without PTADR# ............................................................................................ 139
Figure 73. Active Mode PCI Write without PTADR# ............................................................................................ 140
Figure 74. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT# ....................................... 140
Figure 75. Active Mode 32-Bit PCI Write ............................................................................................................. 141
Figure 76. Active Mode 32-Bit PCI Write w/PTWAIT# ......................................................................................... 142
Figure 77. Active Mode PCI Write Showing a One Wait State Programmed Delay ............................................. 143
Figure 78. 16-Bit Active Mode PCI Read w/ Programmed Wait States ............................................................... 143
Figure 79. Active Mode PCI Read w/ Programmed Wait States .......................................................................... 144
Figure 80. Active Mode PCI Read ....................................................................................................................... 145
Figure 81. Active Mode PCI Write ........................................................................................................................ 145
Figure 82. 8-Bit Active Mode PCI Write ............................................................................................................... 146
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DS1596
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
