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S5920QRC 参数 Datasheet PDF下载

S5920QRC图片预览
型号: S5920QRC
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PQFP160, 28 X 28 MM, 3.37 MM HEIGHT, GREEN, PLASTIC, QFP-160]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 165 页 / 2405 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – April 12, 2007  
S5920 – PCI Product: Operation Registers  
ADD-ON BUS OPERATION REGISTERS  
Data Book  
This register group represents the primary method for  
communication between the Add-On and PCI buses  
as viewed by the Add-On. The flexibility of this  
arrangement allows a number of user-defined soft-  
ware protocols to be built. One should NOT read/write  
from any undefined address, or the read results and  
write effects cannot be guaranteed. Table 6 lists the  
Add-On Bus Operation Registers.  
The Add-On bus interface provides access to 8  
DWORDs of data, control and status information. All of  
these locations are accessed by asserting the Add-On  
bus chip select pin (SELECT#) and the byte-enable  
pins (BE[3:0]), in conjunction with either the read or  
write control enables (signal pin RD# or WR#). All reg-  
isters are accessed with signals synchronous to the  
Add-On clock.  
Table 44. Operation Registers - Add-On Interface  
Address  
0Ch  
1Ch  
28h  
Abbreviation  
AIMB  
Register Name  
Add-On Incoming Mailbox Register  
AOMB  
APTA  
Add-On Outgoing Mailbox Register  
Add-On Pass-Thru Address Register  
Add-On Pass-Thru Data Register  
2Ch  
34h  
APTD  
AMBEF  
AINT  
Add-On Mailbox Empty/Full Status Register  
Add-On Interrupt Control/Status Register  
Add-On Reset Control Register  
38h  
3Ch  
60h  
ARCR  
APTCR  
Add-On Pass-Thru Configuration Register  
AMCC Confidential and Proprietary  
DS1596  
81  
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