Revision 1.02 – April 12, 2007
S5920 – PCI Product: Operation Registers
Data Book
This register provides the method for choosing which
conditions are to produce an interrupt on the Add-On
bus interface, a method for viewing the cause for the
interrupt, and a method for acknowledging (removing)
the interrupt’s assertion.
ADD-ON INTERRUPT CONTROL/STATUS
REGISTER (AINT)
Add-On Interrupt Control and Status
Register Name:
Add-On Address:
Power-up value:
Attribute:
38h
Interrupt sources:
•
•
•
Incoming mailbox becomes full
Outgoing mailbox becomes empty
Built-in self test issued
00000C0Ch
Read/Write, Read/Write Clear
32 bits
Size:
Figure 33. Add-On Interrupt Control Status Register
Interrupt Status
Interrupt Selection
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
31
24
8
432
0
X 0 0 X 0 0 X X 0 0 0
1 1
XX
0 0 0 X 1 1
XX
0 0 0 0
Add-On IMB
(Becomes full)
R/W
D4 = Enable Interrupt
D1 - D0 = Byte Number
00 = Byte 0
01 = Byte 1
10 = Byte 2
11 = Byte 3
Interrupt Asserted (RO)
BIST (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
Add-On OMB (Becomes Empty)
R/W
D12 = Enable Interrupt
D9 - D8 = Byte Number
00 = Byte 0
Incoming Mailbox
Interrupt (R/WC)
01 = Byte 1
10 = Byte 2
11 = Byte 3
AMCC Confidential and Proprietary
DS1596
85
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
