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S5920QRC 参数 Datasheet PDF下载

S5920QRC图片预览
型号: S5920QRC
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PQFP160, 28 X 28 MM, 3.37 MM HEIGHT, GREEN, PLASTIC, QFP-160]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 165 页 / 2405 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – April 12, 2007  
S5920 – PCI Product: Operation Registers  
Data Book  
This register provides empty/full visibility for each byte  
within the mailboxes. The empty/full status for the PCI  
Outgoing mailbox is displayed on bits 15 to 12 and the  
empty/full status for the PCI Incoming mailbox is pre-  
sented on bits 31 to 28. A value of 1 signifies that a  
given mailbox has been written by one bus interface  
but has not yet been read by the corresponding desti-  
nation interface. The PCI bus incoming mailbox  
transfers data from the Add-On bus to the PCI bus,  
and the PCI outgoing mailbox transfers data from the  
PCI bus to the Add-On bus. This register is also  
referred to as the Add-On Mailbox Empty/Full Status  
Register (AMBEF).  
PCI MAILBOX EMPTY/FULL STATUS REG-  
ISTER (MBEF)  
Mailbox Empty/Full Status  
Register Name:  
PCI Address Offset:  
Power-up value:  
PCI Attribute:  
Size:  
34h  
00000000h  
Read Only  
32 bits  
Figure 28. Mailbox Empty/Full Status Register (MBEF)  
31  
28 27  
16 15  
12 11  
0
0000  
0000  
Reserved  
Reserved  
PCI Outgoing  
Mailbox Status (RO)  
PCI Incoming  
Mailbox Status (RO)  
Table 40. Mailbox Empty/Full Status Register  
Bit  
Description  
31:28  
PCI Incoming Mailbox Status. This field indicates which byte of the incoming mailbox register has been written  
by the Add-On interface but has not been read by the PCI bus. Each bit location corresponds to a specific byte  
within the incoming mailbox. A value of one for each bit signifies that the specified mailbox byte is full, and a  
value of 0 signifies empty. The mapping of these status bits to bytes within the mailbox is as follows:  
Bit 31 = Incoming mailbox byte 3  
Bit 30 = Incoming mailbox byte 2  
Bit 29 = Incoming mailbox byte 1  
Bit 28 = Incoming mailbox byte 0  
15:12  
PCI Outgoing Mailbox Status. This field indicates which byte of the outgoing mailbox register has been written  
by the PCI bus interface but has not yet been read by the Add-On bus. Each bit location corresponds to a spe-  
cific byte within the outgoing mailbox. A value of one for each bit signifies that the specified mailbox byte is full,  
and a value of 0 signifies empty. The mapping of these status bits to bytes is as follows:  
Bit 15 = Outgoing mailbox byte 3  
Bit 14 = Outgoing mailbox byte 2  
Bit 13 = Outgoing mailbox byte 1  
Bit 12 = Outgoing mailbox byte 0  
AMCC Confidential and Proprietary  
DS1596  
74  
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