Revision 1.02 – April 12, 2007
S5920 – PCI Product: Operation Registers
Data Book
This register configures the conditions which will pro-
duce an interrupt on the PCI bus interface, a method
for viewing the cause of the interrupt, and a method for
acknowledging (removing) the interrupt’s assertion.
PCI INTERRUPT CONTROL/STATUS REG-
ISTER (INTCSR)
Interrupt Control and Status
Register Name:
PCI Address Offset:
Power-up value:
PCI Attribute:
Size:
Interrupt sources:
38h
•
•
•
The Outgoing mailbox becomes empty.
The Incoming mailbox becomes full.
Add-On interrupt pin enable and flag.
00000C0Ch
Read/Write, Read/Write Clear
32 bits
Figure 29. Interrupt Control Status Register
Actual Interrupt
Interrupt Selection
3
1
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8 75
432
X 1
1
0
X X 0
0
0
0
X X 0
0
X X 1
1
XX
000
1
XX
00000000
Interrupt Asserted (RO)
Interrupt Source (R/W)
Enable & Selection
Add-On Interrupt Pin
(ADDINT#) Status (RO)
D4 - D0 PCI Outgoing Mailbox
(Becomes Empty)
D4 = Enable Interrupt
D1 - D0 = Byte Number
00 = Byte 0
Incoming Mailbox
Interrupt (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
01 = Byte 1
D8 - D12 PCI Incoming Mailbox
D12 = Enable Interrupt
D9 - D8 = Byte Number
00 = Byte 0
10 = Byte 2
11 = Byte 3
Add-On Interrupt Pin
(ADDINT#) Enable
(R/W)
01 = Byte 1
10 = Byte 2
11 = Byte 3
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DS1596
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
