Revision 1.02 – April 12, 2007
S5920 – PCI Product: PCI Configuration Registers
Data Book
This register may be optionally used by bus masters to
specify how often this device needs PCI bus access. A
value of zero indicates that the bus master has no
stringent requirement. The units defined by the least
significant bit are in 250 ns increments. Since the
S5920 is a PCI target device only, this register is
treated as “information only” and has no further imple-
mentation within this device.
MAXIMUM LATENCY REGISTER (MAX-
LAT)
Maximum Latency
3Fh
Register Name:
Address Offset:
Power-up value:
Boot-load:
00h, hardwired
not used
Read Only
8 bits
Attribute:
Size:
Figure 25. Maximum Latency Register
Bit
7
0
Value
00h
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DS1596
70
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
