Revision 1.02 – April 12, 2007
S5920 – PCI Product: Signal Description
Data Book
Table 19. S5920 Add-On Bus Register Access Pins
Signal
Type
Description
DQ[31:0]
t/s
Address/Data bus. The 32-bit Add-On data bus. The DQMODE signal configures the bus width for
either 32 or 16 bits. All DQ[31:0] signals have an internal pull-up.
ADR[6:2]
in
Address [6:2]. These inputs select which S5920 register is to be read from or written to. To be used
in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The register addresses are as follows:
ADR[6:2]
0 0 0 1 1
0 0 1 1 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
Register Name
Add-On Incoming Mailbox Register
Add-On Outgoing Mailbox Register
Add-On Pass-Thru Address Register
Add-On Pass-Thru Data Register
Add-On Mailbox Status Register
Add-On Interrupt Control Register
Add-On Reset ControlRegister
Pass-Thru/FIFO Configuration Register
Note: ADR[6:2] bits begin at bit position two. All references to an address, in hex, adds bits 0 and 1
as zeros. Example: The Add-On incoming mailbox register is referenced as 0Ch.
BE[2:0]#
in
in
Byte Enable 2 through 0. Provides individual read/write byte enabling during register read or write
transactions. BE2# enables activity over DQ[23:16], BE1# enables DQ[15:8], and BE0# enables
DQ[7:0]. During read transactions, these pins enable the output driver for each byte lane; for write
transactions, they serve as an input enable to perform the write to each byte lane.
BE3# / ADR1
Byte Enable [3] for a 32-bit bus width / Address [1] for a 16-bit bus width. BE3#, enables DQ[31:24]
input drivers for writing data to registers identified by ADR[6:2] and enables DQ[31:24] output driv-
ers to read registers identified by ADR[6:2]. To be used in conjunction with SELECT# and RD# or
WR#. ADR1, selects the upper or lower WORD of a DWORD when a 16-bit-wide bus is selected. 1
= upper, 0 = lower.
SELECT#
WR#
in
in
in
in
Select. Enables internal S5920 logic to decode WR#, RD# and ADR[6:2] when reading or writing to
any Add-On register.
Write Enable. Asserting this signal writes DQ bus data byte(s) selected by BE[3:0]# into the S5920
register defined by SELECT# and ADR[6:2].
RD#
Read Enable. Asserting this signal drives data byte(s) selected by BE[3:0]# from the S5920 register
defined by SELECT# and ADR[6:2] onto the DQ bus.
DQMODE
DQ Mode. Defines the DQ bus width when accessing data using WR#, RD#, SELECT# and
ADR[6:2]#. Low = 32-bit wide DQ bus. High = 16-bit wide DQ bus. When high, the signal BE3# is re-
assigned to the ADR1 signal and only DQ[15:0] is active.
Note: This pin only affects DQ Bus Width for S5920 Data Registers. This pin has no effect on
accesses DQ Bus Width. For the Pass-Thru data register (APTD, ADR = 2Ch). The width of the DQ
bus is determined by the region-size bits in the corresponding Base Address Register. In addition,
DQMODE has no effect when using the direct-access pin PTADR#. When PTADR# is asserted, all
32 bits of the Pass-Thru address are provided.
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