Revision 1.02 – April 12, 2007
S5920 – PCI Product: Mailbox Overview
Data Book
4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The
request is cleared by writing a 1 to the appropriate bit.
AINT
AINT
Bit 17
Bit 16
Clear Add-On outgoing mailbox interrupt
Clear Add-On incoming mailbox interrupt
NOTE: For an incoming mailbox interrupt, step 3 involves accessing the mailbox. To allow the incoming mailbox
interrupt logic to be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the
status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the RCR and ARCR
registers, but this clears all status bits, not just a single mailbox byte. For outgoing mailbox interrupts, the status bit
was already cleared prior to the generation of the interrupt. As a result, the mailbox does not need to be read.
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