Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI Controlled Bus Master Write Transfer Count
Register (MWTC)
The master write transfer count register is used to con-
vey to the S5335 controller the actual number of bytes
that are to be transferred. The value in this register is
decremented with each bus master PCI write opera-
tion until the transfer count reaches zero.
Master Write Transfer Count
Register Name:
PCI Address Offset:
Power-up value:
Attribute:
28h
Upon reaching zero, the transfer operation ceases and
an interrupt may be optionally generated to either the
PCI or Add-On bus interface. Transfers which are not
whole multiples of DWORDs in size result in a partial
word ending cycle. This partial word ending cycle is
possible since all bus master transfers for this control-
ler are required to begin on a DWORD boundary.
00000000h
Read/Write
32 bits
Size:
Under certain circumstances, MWTC can be accessed
from the Add-On bus instead of the PCI bus. See Add-
On Initiated Bus Mastering.
Figure 25. PCI Controlled Bus Master Write Transfer Count Register
31
26 25
0
Bit
Value
00
Transfer Count
in Bytes (R/W)
Reserved = O's (RO)
AMCC Confidential and Proprietary
DS1657 58
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
