Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI Controlled Bus Master Write Address Register
(MWAR)
Note: Applications which require a non-DWORD start-
ing boundary will need to move the first few bytes
under software program control (and without using the
FIFO) to establish a DWORD boundary. After the
DWORD boundary is established the S5335 can begin
the task of PCI bus master data transfers.
Master Write Address
24h
Register Name:
PCI Address Offset:
Power-up value:
Attribute:
00000000h
Read/Write
32 bits
The Master Write Address Register is continually
updated during the transfer process and will always be
pointing to the next unwritten location. Reading of this
register during a transfer process (done when the
S5335 controller is functioning as a target, i.e. not a
bus master) is permitted and may be used to monitor
the progress of the transfer. During the address phase
for bus master write transfers, the two least significant
bits presented on the PCI bus pins AD[31:0] will
always be zero. This identifies to the target memory
that the burst address sequence will be in a linear
order rather than in an Intel 486 or Pentium™ cache
line fill sequence. Also, the PCI bus address bit A1 will
always be zero when this controller is the bus master.
This signifies to the target that the S5335 controller is
burst capable and that the target should not arbitrarily
disconnect after the first data phase of this operation.
Size:
This register is used to establish the PCI address for
data moving from the Add-On bus to the PCI bus dur-
ing PCI bus memory write operations. It consists of a
30-bit counter with the low-order two bits hardwired as
zeros. Transfers may be any non-zero byte length as
defined by the transfer count register, MWTC, and
must begin on a DWORD boundary. This DWORD
boundary starting constraint is placed upon this con-
troller’s PCI bus master transfers so that byte lane
alignment can be maintained between the S5335 con-
troller’s internal FIFO data path, the Add-On interface,
and the PCI bus.
Under certain circumstances, MWAR can be accessed
from the Add-On bus instead of the PCI bus. See Add-
On Initiated Bus Mastering.
Figure 24. PCI Controlled Bus Master Write Address Register
31
2
1
0
0
0
Bit
Value
DWORD Address (RO)
Write Transfer Address (R/W)
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