Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Outgoing Mailbox Registers (OMB)
These four DWORD registers provide a method for sending command or
parameter data to the Add-On system. PCI bus operations to these regis-
ters may be in any width (byte, word, or DWORD). Writing to these regis-
ters can be a source for Add-On bus interrupts (if desired) by enabling
their interrupt generation through the use of the Add-On’s interrupt con-
trol/status register.
Outgoing Mailboxes 1-4
00h, 04h, 08h, 0Ch
XXXXXXXXh
Register Names:
PCI Address Offset:
Power-up value:
Attribute:
Read/Write
32 bits
Size:
Incoming Mailbox Registers (IMB)
These four DWORD registers provide a method for receiving user
defined data from the Add-On system. PCI bus read operations to these
registers may be in any width (byte, word, or DWORD). Only read opera-
tions are supported. Reading from these registers can optionally cause
an Add-On bus interrupt (if desired) by enabling their interrupt generation
through the use of the Add-On’s interrupt control/status register. Mailbox
4, byte 3 only exists as device pins on the S5335 devices when used with
a serial nonvolatile memory.
Incoming Mailboxes 1-4
Register Names:
PCI Address Offset:
Power-up value:
Attribute:
10h, 14h, 18h, 1Ch
XXXXXXXXh
Read Only
32 bits
Size:
FIFO Register Port (FIFO)
This location provides access to the bidirectional FIFO. Separate regis-
ters are used when reading from or writing to the FIFO. Accordingly, it is
not possible to read what was written to this location. The FIFO registers
are implicitly involved in all bus master operations and, as such, should
not be accessed during active bus master transfers. When operating
upon the FIFOs with software program transfers involving word or byte
operations, the endian sequence of the FIFO should be established as
described under FIFO Endian Conversion Management in order to pre-
serve the internal FIFO data ordering and flag management. The FIFO’s
fullness may be observed by reading the master control-status register or
MCSR register.
FIFO Port
Register Name:
PCI Address Offset:
Power-up value:
Attribute:
20h
XXXXXXXXh
Read/Write
Size:
32 bits
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DS1657 56
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
