Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
CONFIGURATION
Data Sheet
D31
0
D30
0
Add-On Bus Width
The S5335 Pass-Thru interface utilizes four Base
Address Registers (BADR1:4). Each Base Address
Register corresponds to a Pass-Thru region. The con-
tents of these registers during initialization determine
the characteristics of that particular Pass-Thru region.
Each region can be mapped to memory or I/O space.
Memory mapped devices can, optionally, be mapped
below 1 Mbyte and can be identified as prefetchable.
Both memory and I/O regions can be configured as 8-,
16-, or 32-bits wide.
Region disabled
8-bits
0
1
1
0
16-bits
1
1
32-bits
BADR1:4 bits D31:30 are used only by the S5335.
When the host reads the Base Address Registers dur-
ing configuration cycles, they always return the same
value as D29. If D29 is zero, D31:30 return zero, indi-
cating the region is disabled. If D29 is one, D31:30
return one. This operation limits each Pass-Thru
region to a maximum size of 512 Mbytes of memory.
The designer has the option to use 1, 2, 3, 4 or none of
the Pass-Thru regions. Base Address Registers are
loaded during initialization from the external non-vola-
tile boot device. Without an external boot device, the
default value for the BADR registers is zero (region
disabled). The Base Address Registers are the only
registers that define Pass-Thru operation.
For I/O mapped regions, the PCI specification allows
no more than 256 bytes per region. The S5335 allows
larger regions to be requested by the Add-On, but a
PCI BIOS will not allocate the I/O space and will prob-
ably disable the region.
S5335 Base Address Register Definition
Some bits in the Base Address Registers have specific
functions. The following bits have special functions:
Creating a Pass-Thru Region
Page 3-40 describes the values that must be pro-
grammed into the non-volatile boot device to request
various block sizes and characteristics for Pass-Thru
regions. After reset, the S5335 downloads the con-
tents of the boot device locations 54h, 58h, 5Ch, and
60h into “masks” for the corresponding Base Address
Registers. The following are some examples for vari-
ous Pass-Thru region definitions:
D0
Memory or I/O mapping. If this bit is clear, the
region should be memory mapped. If this bit is
set, the region should be I/O mapped.
D2:1
Location of a memory region. These bits
request that the region be mapped in a particu-
lar part of memory. These bit definitions are
only used for memory mapped regions.
D3
Prefetchable. For memory mapped regions,
the region can be defined as cacheable. If set,
the region is cacheable. If this bit is clear, the
region is not.
NV Memory
Contents
Pass-Thru Region Definition
54h = BFFFF002h Pass-Thru region 1 is a 4Kbyte
region, mapped below 1 Mbyte in
memory space with a 16-bit Add-On
data bus. This memory region is not
cacheable.
D31:30 Pass-Thru region bus width. These two bits are
used by the S5335 to define the data bus width
for a Pass-Thru region. Regardless of the pro-
gramming of other bits in the BADR register, if
D31:30 are zeros, the Pass-Thru region is dis-
abled.
58h = 3xxxxxxxh
Pass-Thru region 2 is disabled.
(D31:30 = 00.)
60h = FFFFFF81h Pass-Thru region 3 is a 32-bit, 128
byte I/O-mapped region.
D2 D1
Location
0
0
0
1
Anywhere in 32-bit memory space
64h = 00000000h
Pass-Thru region 4 is disabled.
Below 1 Mbyte in memory space (Real Mode
address space)
During the PCI bus configuration, the host CPU writes
all ones to each Base Address Register, and then
reads the contents of the registers back. The mask
downloaded from the boot device determines which
bits are read back as zeros and which are read back
1
1
0
1
Anywhere in 64-bit memory space (not valid
for the S5335)
Reserved
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DS1657 161
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
