Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 91. Target Requested Retry after the First Data Phase of a Burst Operation
1
6
7
8
PCICLK
FRAME#
STOP#
0
1
2
7
8
9
BPCLK
PTATN#
PTRDY#
PCI Data Transfer
Latest assertion of PTRDY#
to prevent disconnect
PTRDY# asserted too late,
results in disconnect
The previous data phase is completed with the asser-
tion of PTRDY# at the rising edge of BPCLK 0. Add-
On logic must assert PTRDY# by the rising edge of
BPCLK 8 to prevent the S5335 from asserting STOP#,
requesting a retry. Meeting this condition allows the
S5335 to assert TRDY# by the rising edge of PCICLK
8, completing the data phase with requiring a retry.
For Pass-Thru write operations, one or two data trans-
fers may remain after the S5335 signals a retry. Two
data transfers are possible because the S5335 has a
double buffered Pass-Thru data register used for
writes. A PCI burst may have filled both registers
before the S5335 requested a retry. PTATN# remains
asserted until both are emptied. PTRDY# must be
asserted after each read from the Pass-Thru data reg-
ister. If both registers are full, PTATN# is deasserted
only after PTRDY# is asserted the second time. The
S5335 only accepts further PCI accesses after both
registers are emptied.
When the S5335 requests a retry, the Pass-Thru sta-
tus indicators remain valid (allowing the Add-On logic
to complete the access). PTBURST# is the exception
to this. PTBURST# is deasserted to indicate that there
is currently no burst in progress on the PCI bus. The
other Pass-Thru status indicators remain valid until
PTATN# is deasserted. Figure 92 shows the Add-On
bus interface signals after the S5335 requests a retry.
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface
The S5335 allows a simple interface to devices with 8-
bit or 16-bit data buses. Each Pass-Thru region may
be defined as 8-, 16-, or 32-bits, depending on the
contents of the nv memory boot device loaded into the
PCI Base Address Configuration Registers during ini-
tialization. The Pass-Thru Add-On interface internally
controls byte lane steering to allow access to the 32-
bit Pass-Thru Data Register (APTD) from 8-bit or 16-
bit Add-On buses.
As long as PTATN# remains asserted, Add-On logic
should continue to transfer data. For PCI read opera-
tions, one Add-On write operation is required after a
retry request. After the Add-On write, asserting
PTRDY# deasserts PTATN#.
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