Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On Pass-Thru Disconnect Operation
phase of a PCI read operation. FRAME# is asserted
during the rising edge of PCI clock 1. From this point,
the S5335 has 16 clock cycles to respond to the initia-
tor with TRDY# (completing the cycle). FRAME# could
remain asserted, indicating a burst read, but the retry
request conditions are identical for a single data phase
read and the first data phase of a burst read. BPCLK is
identical to PCICLK, lagging by a propagation delay of
a few nanoseconds (see Chapter 13). PTATN# is
asserted on the Add-On interface as soon as FRAME#
is sampled active at a PCICLK rising edge.
Slow PCI targets are prevented from degrading PCI
bus performance. The PCI specification allows only 16
clocks for a target to respond before it must request a
retry on single data phase accesses. For burst
accesses, the first data phase is allowed 16 clocks to
complete, all subsequent data phases are allowed 8
clocks each. This requirement allows other PCI initia-
tors to use the bus while the target requesting the retry
completes the original access.
Figure 90 shows the conditions that cause the S5335
to request a retry from a PCI initiator on the first data
Figure 90. Target Requested Retry on the First PCI Data Phase
1
2
3
4
15
14
16
15
17
16
18
17
PCICLK
FRAME#
STOP#
1
2
3
BPCLK
PTATN#
PTRDY#
PTRDY#must beassertedby
this time topresent disconnecting
PTRDY# assertedtoo lateso
S5335 disconnects (asserts STOP#)
After PTATN# is asserted, PTRDY# must be asserted
by the 15th BPCLK rising edge to prevent the S5335
from requesting a retry. TRDY# is asserted on the PCI
interface one clock cycle after PTRDY# is asserted on
the Add-On interface. If Add-On logic does not return
PTRDY# by the 15th BPCLK rising edge, the S5335
asserts STOP#, requesting a retry from the PCI
initiator.
burst. The first data and second phases are always
accepted immediately by the S5335. No further action
is required by the PCI initiator. The only situation
where the S5335 may respond to a Pass-Thru write
with a retry request is after the second data phase of a
Pass-Thru burst write.
Figure 91 shows the conditions required for the S5335
to request a retry after the second data phase of a
burst transfer. This figure applies to both Pass-Thru
burst read and write operations.
For Pass-Thru write operations, the S5335 never dis-
connects on the first or second PCI data phases of a
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