Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
The optional nvRAM allows the Add-On card manufac-
turer to initialize the S5335 with his specific Vendor ID
and Device ID numbers along with desired S5335
operation characteristics. The non-volatile memory
feature also provides for the Expansion BIOS and
POST code (power-on-self-test) options on the PCI
bus.
Mailbox Operation
The Mailbox Registers are divided into two four
DWORD sets. Each set is dedicated to one bus for
transferring data to the other bus. Figure 4 below
shows a block diagram of the mailbox section of the
S5335. The provision of Mailbox Registers provides
an easy path for the transfer of user information (com-
mand, status or parametric data) between the two
buses. An empty/full indication for each Mailbox Reg-
ister, at the byte level, is determined by polling a
Status Register accessible to both the PCI and Add-
On buses. Providing Mailbox byte level empty/full indi-
cations allows for greater flexibility in 8-, 16- or 32-bit
system interfaces. i.e., transferring a single byte to an
8-bit Add-On bus without requiring the assembling or
disassembling of 32-bit data.
Table 3. Add-On Bus Operation Registers
Add-On Bus Operation Registers
Incoming Mailbox Register 1 (AIMB1)
Incoming Mailbox Register 2 (AIMB2)
Incoming Mailbox Register 3 (AIMB3)
Incoming Mailbox Register 4 (AIMB4)
Outgoing Mailbox Register 1 (AOMB1)
Outgoing Mailbox Register 2 (AOMB2)
Outgoing Mailbox Register 3 (AOMB3)
Outgoing Mailbox Register 4 (AOMB4)
FIFO Port (AFIFO)
Address
00h
04h
08h
0Ch
10h
The generation of interrupts from Mailbox Registers is
equivalent with the commonly known ‘DOORBELL’
interrupt technique. Bit locations configured within the
S5335’s Operation Registers select a Mailbox and
Mailbox byte which is to generate an interrupt when
full or touched. A mailbox interrupt control register is
then used to enable interrupt generation and to select
if the interrupt is to be generated on the PCI or Add-On
Local bus. PCI Local bus interrupts may also be gen-
erated from direct hardware interfacing due to a
unique AMCC feature. A dedicated Mailbox byte is
directly accessible via a set of hardware device signal
pins. A mailbox load signal pin latches Add-On bus
data directly into the Mailbox initiating a PCI bus inter-
rupt if enabled. Mailbox data may also be read in a
similar manner. This option is shared with the byte
wide non-volatile memory signal pins. The S5335
must use the serial nvRAM for the direct mailbox
option signal pins to be available or they are assigned
to the byte wide at power up.
14h
18h
1Ch
20h
Bus Master Write Address Register (MWAR)
Pass-Thru Address Register (APTA)
Pass-Thru Data Register (APTD)
24h
28h
2Ch
30h
Bus Master Read Address Register (MRAR)
Mailbox Empty/Full Status Register (AMBEF)
Interrupt Control/Status Register (AINT)
General Control/Status Register (ARCR)
Bus Master Write Transfer Count (MWTC)
Bus Master Read Transfer Count (MRTC)
34h
38h
3Ch
58h
5Ch
AMCC Confidential and Proprietary
DS1657 15
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
