Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 1. PCI Configuration Registers (Continued)
Table 2. PCI Operation Registers
Byte 3
Byte 2
Byte 1
Byte 0
Address
04h
Address
Offset
PCI Operation Registers
PCI Status
Class Code
PCI Command
Revision ID
Outgoing Mailbox Register 1 (OMB1)
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
08h
Outgoing Mailbox Register 2 (OMB2)
Outgoing Mailbox Register 3 (OMB3)
Outgoing Mailbox Register 4 (OMB4)
Incoming Mailbox Register 1 (IMB1)
Built-in
Self Test
Header
Type
Latency
Timer
Cache
Line Size
0Ch
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Reserved
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
Incoming Mailbox Register 2 (IMB2)
Incoming Mailbox Register 3 (IMB3)
Incoming Mailbox Register 4 (IMB4)
FIFO Register Port (bidirectional) (FIFO)
Master Write Address Register (MWAR)
Master Write Transfer Count Register (MWTC)
Master Read Address Register (MRAR)
Master Read Transfer Count Register (MRTC)
Mailbox Empty/Full Status Register (MBEF)
Interrupt Control/Status Register (INTCSR)
Bus Master Control/Status Register (MCSR)
Reserved Space
Reserved Space
Expansion ROM Base Address
Reserved Space
Reserved Space
Max.
Latency
Min. Grant
Interrupt
Pin
Interrupt
Line
PCI Operation Registers
Add-On Bus Operation Registers
The second group of registers are the PCI Operation
Registers shown in Table 2. This group consists of six-
teen 32-bit (DWORD) registers accessible to the Host
processor from the PCI Local bus. These are the main
registers through which the PCI Host configures
S5335 operation and communicates with the Add-On
Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel,
Bus Master Address and Count registers, Pass-Thru
data channel registers and S5335 device Status and
Control registers.
The third and last register group consists of the Add-
On Operation Registers, shown in Table 3. This group
of eighteen 32-bit (DWORD) registers is accessible to
the Add-On Local bus. These are the main registers
through which the Add-On logic configures S5335
operation and communicates with the PCI Local bus.
These registers encompass the Add-On bus Mail-
boxes, Add-On FIFO, DMA Address/Count Registers
(when Add-On initiated Bus Mastering), Pass-Thru
Registers and Status/Control registers.
Non-Volatile Memory Interface
The S5335 contains a set of PCI Configuration Regis-
ters. These registers can be initialized with default
values or with designer specified values contained in
an external nvRAM. The nvRAM can be either a serial
(2 Kbytes, maximum) or a byte-wide device (64
Kbytes, maximum).
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