Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Table 40. Read Response (I/O Assigned) to an All-Ones write Operation to a Base Address Register ............... 48
Table 41. Expansion ROM Base Address Register ............................................................................................... 49
Table 42. Read Response to Expansion ROM Base Address Register (after all-ones written) ............................. 50
Table 43. Operation Registers — PCI Bus ............................................................................................................ 55
Table 44. Mailbox Empty/Full Status Register ....................................................................................................... 62
Table 45. Interrupt Control/Status Register ........................................................................................................... 65
Table 46. Bus Master Control/Status Register ....................................................................................................... 68
Table 47. Operation Registers — Add-On Interface .............................................................................................. 70
Table 48. Add-On Mailbox Empty/Full Status Register .......................................................................................... 76
Table 49. Interrupt Control/Status Register ........................................................................................................... 78
Table 50. Add-On General Control/Status Register ............................................................................................... 81
Table 51. Valid External Boot Memory Contents ................................................................................................... 86
Table 52. PC Compatible Expansion ROM ............................................................................................................ 90
Table 53. PCI Data Structure ................................................................................................................................. 91
Table 54. Supported PCI Bus Commands ............................................................................................................. 93
Table 55. Target Termination Types .................................................................................................................... 101
Table 56. Possible Combinations of FRAME# and IRDY# .................................................................................. 104
Table 57. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) .................................................... 159
Table 58. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read) .................................................... 159
Table 59. Absolute Maximum Ratings ................................................................................................................. 163
Table 60. Recommended Operating Conditions and DC Electrical Characteristics ............................................ 163
Table 61. PCI Bus Signals ................................................................................................................................... 164
Table 62. Add-On Bus Signals ............................................................................................................................. 165
Table 63. PCI Bus Timing .................................................................................................................................... 166
Table 64. Synchronous RDFIFO# Timing ............................................................................................................ 169
Table 65. Synchronous WRFIFO Timing ............................................................................................................. 170
Table 66. Asynchronous RD# Register Access Timing ....................................................................................... 171
Table 67. Asynchronous WR# Register Access Timing ....................................................................................... 172
Table 68. Synchronous RD# FIFO Timing ........................................................................................................... 173
Table 69. Synchronous WR# FIFO Timing .......................................................................................................... 175
Table 70. Pass-Thru Interface Timing .................................................................................................................. 177
Table 71. Target Byte-Wide Memory Interface Timing ........................................................................................ 179
Table 72. Target Interrupt Timing ........................................................................................................................ 181
Table 73. MailBox Timing .................................................................................................................................... 181
Table 74. S5335 Numerical Pin Assignment - 176 LQFP .................................................................................... 184
AMCC Confidential and Proprietary
DS1657 12
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
