Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
For bus master transfers initiated by the Add-On inter-
face, some applications may not know the size of the
data block to be transferred. To avoid constantly
updating the transfer count register, the transfer count
may be disabled. Bit 28 in the Add-On General Con-
trol/Status Register (AGCSTS) performs this function.
Disabling the transfer count also disables the interrupt
capabilities. Regardless of whether Add-On transfer
count is enabled or disabled, the Add-On Master Read
Enable (AMREN) and Add-On Master Write Enable
(AMWEN) inputs control when the S5335 asserts or
deasserts its request to the PCI bus. When Add-On
transfer count is enabled, the S5335 will only request
the bus when both the transfer count (read or write) is
not zero and the appropriate enable line (AMREN or
AMWEN) is active. For Add-On initiated bus master-
ing, AMWEN and AMREN override the read and write
bus mastering enable bits in the Bus Master Control/
Status Register (MCSR).
written before or after bus mastering is enabled. If bus
mastering is enabled, no transfer occurs until the
transfer count is programmed with a non-zero value.
Once a transfer begins, this register is automatically
updated to reflect the number of bytes remaining to be
transferred. If the transfer count registers are disabled
(for Add-On initiated bus mastering), transfers begin
as soon as bus mastering is enabled.
Although transfers must begin on DWORD bound-
aries, transfer counts do not have to be multiples of
four bytes. For example, if the write transfer count
(MWTC) register is programmed with a value of 10
(decimal), the S5335 performs two DWORD writes
and a third write with only BE0# and BE1# asserted.
Bus Mastering FIFO Management Schemes
The S5335 provides flexibility in how the FIFO is man-
aged for bus mastering. The FIFO management
scheme determines when the S5335 requests the bus
to initiate PCI bus cycles. The management scheme is
configurable for the PCI to Add-On and Add-On to PCI
FIFO (and may be different for each). Bus mastering
must be enabled for the management scheme to apply
(via the enable bits or AMREN/AMWEN).
PCI Initiated Bus Mastering
If bit 7 in location 45h of the external non-volatile mem-
ory is one, the Master Read Address Register
(MRAR), Master Write Address Register (MWAR),
Master Read Transfer Count (MRTC), and Master
Write Transfer Count (MWTC) are accessible only
from the PCI bus interface. In this configuration, the
S5335 transfers data until the transfer count reaches
zero. The transfer count cannot be disabled for PCI
initiated bus mastering. If no external nv memory boot
device is used, the S5335 defaults to PCI initiated bus
mastering.
For the PCI to Add-On FIFO, there are two manage-
ment options. The PCI to Add-On FIFO management
option is programmed through the Bus Master Control/
Status Register (MCSR). The FIFO can be pro-
grammed to request the bus when any DWORD
location is empty or only when four or more locations
are empty. After the S5335 is granted control of the
PCI bus, the management scheme does not apply.
The device continues to read as long as there is an
open FIFO location. When the PCI to Add-On FIFO is
full or bus mastering is disabled, the PCI bus request
is removed by the S5335.
Address and Transfer Count Registers
The S5335 has two sets of registers used for bus mas-
ter transfers. There are two operation registers for bus
master read operations and two operation registers for
bus master write operations. One operation register is
for the transfer address (MWAR and MRAR). The
other operation register is for the transfer byte count
(MWTC and MRTC).
For the Add-On to PCI FIFO, there are two manage-
ment options. The Add-On to PCI FIFO management
option is programmed through the Bus Master Control/
Status Register (MCSR). The FIFO can be pro-
grammed to request the bus when any DWORD
location is full or only when four or more locations are
full. After the S5335 is granted control of the PCI bus,
the management scheme does not apply. The device
continues to write as long as there is data in the FIFO.
When the Add-On to PCI FIFO is empty or bus mas-
tering is disabled, the PCI bus request is removed by
the S5335.
The address registers are written with the first address
of the transfer before bus mastering is enabled. Once
a transfer begins, this register is automatically updated
to reflect the address of the current transfer. If a PCI
target disconnects from an S5335 initiated cycle, the
transfer is retried starting from the current address in
the register. If bus grant (GNT#) is removed or bus
mastering is disabled (using AMREN or AMWEN), the
value in the address register reflects the next address
to be accessed. Transfers must begin on DWORD
boundaries.
There are two special cases for the Add-On to PCI
FIFO management scheme. The first case is when the
FIFO is programmed to request the PCI bus only when
four or more locations are full, but the transfer count is
less than 16 bytes. In this situation, the FIFO ignores
The transfer count registers contain the number of
bytes to be transferred. The transfer count may be
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