Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI Configuration Space Header
31
24 23
DEVICE ID
STATUS
16 15
8 7
00
VENDOR ID
COMMAND
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
REV ID
CACHE LINE SIZE
CLASS CODE
HEADER TYPE = 0
BIST
LATENCY TIMER
BASE ADDRESS REGISTER #0
BASE ADDRESS REGISTER #1
BASE ADDRESS REGISTER #2
BASE ADDRESS REGISTER #3
BASE ADDRESS REGISTER #4
BASE ADDRESS REGISTER #5
RESERVED = 0's
RESERVED = 0's
EXPANSION ROM BASE ADDRESS
RESERVED = 0's
RESERVED = 0's
MAX_LAT
MIN_GNT
INTERRUPT PIN
INTERRUPT LINE
LEGEND
EPROM IS DATA SOURCE (READ ONLY)
CONTROL FUNCTION
EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT)
EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT)
HARD-WIRED TO ZEROES
Note: Some registers are a combination of the above. See individual sections
for full description.
AMCC Confidential and Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
