Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On Pass-Thru Address Register (APTA)
This register is employed when a response is desired when
one of the Base address decode regions is selected during an
active PCI bus cycle. When one of the base address decode
registers 1-4 encounters a PCI bus cycle which selects the
region defined by it, this device latches that current cycle’s
active address and asserts the signal PTATN# (Pass-Thru
Attention). Wait states are generated on the PCI bus until
either data is transferred or the PCI bus cycle is aborted by the
initiator.
Add-On Pass-Thru Address
28h
Register Name:
Add-On Address Offset:
Power-up value:
Attribute:
XXXXXXXXh
Read Only
Size:
This register provides a method for “live” data (registered)
transfers. Intended uses include the emulating of other hard-
ware as well as enabling the connection of existing external
hardware to interface to the PCI bus through the S5335.
32 bits
Add-On Pass-thru Data Register (APTD)
This register, along with APTA described above, is employed when
a response is desired should one of the Base address decode
regions become selected during an active PCI bus cycle. When one
of the base address decode registers 1-4 encounters a PCI bus
cycle which selects the region defined by it, the APTA register will
contain that current cycle’s active address and the device asserts
the signal PTATN# (Pass-Thru ATentioN). Wait states are generated
on the PCI bus until this register is read (PCI bus writes) or this reg-
ister is written (PCI bus reads).
Add-On Pass-Thru Data
Register Name:
Add-On Address Offset:
Power-up value:
Attribute:
2Ch
XXXXXXXXh
Read/Write
32 bits
Size:
AMCC Confidential and Proprietary
DS1657 73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
