Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Add-On Incoming Mailbox Registers (AIMBx)
Add-On Incoming Mailboxes These four DWORD registers provide a method for receiving
Register Names:
1-4
data, commands, or command parameters from the PCI inter-
face. Add-On read operations to these registers may be in any
width (byte, word, or DWORD). These registers are read-only.
Writes to this address space have no effect. Reading from one
of these registers can optionally cause a PCI bus interrupt (if
desired) when the PCI interrupt control/status register is prop-
erly configured.
00h, 04h, 08h, 0Ch
Add-On Address Offset:
Power-up value:
Attribute:
XXXXXXXXh
Read Only
32 bits
Size:
Add-On Outgoing Mailbox Registers (AOMBx)
Add-On Outgoing Mailboxes These four DWORD registers provide a method for sending
Register Names:
1-4
data, commands, or command parameters or status to the PCI
interface. Add-On write operations to these registers may be in
any width (byte, word, or DWORD). These registers may also
be read. Writing to one of these registers can optionally cause a
PCI bus interrupt (if desired) when the PCI interrupt control/sta-
tus register is properly configured. Mailbox 4, byte 3 only exists
as device pins on the S5335 device when used with a serial
nonvolatile memory. This byte is not available if a byte-wide nv
memory is used.
10h, 14h, 18h, 1Ch
Add-On Address Offset:
Power-up value:
Attribute:
XXXXXXXXh
Read/Write
32 bits
Size:
Add-On FIFO Register Port (AFIFO)
Add-On FIFO Port This location provides access to the bidirectional FIFO. Separate registers
are involved when reading and writing to this location. Accordingly, it is not
Register Name:
Add-On Address Offset:
Power-up value:
Attribute:
20h
possible to read what was written to this location. The sequence of filling
and emptying this FIFO is established by the PCI interface interrupt con-
trol and Status Register.
XXXXXXXXh
Read/Write
32 bits
The FIFO’s fullness may be observed by reading the master control/status
register or AGCSTS register Additionally, two signal pins are provided
which reveal whether data is available (RDEMPTY) or space to write into
the FIFO is available (WRFULL). These signals may be used to interface
with user supplied DMA logic. Caution must be exercised when using
these flags for FIFO transfers involving 64 bit endian conversion since the
FIFO must operate on DWORD pairs.
Size:
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DS1657 71
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