SONET/SDH OC-12 TO OC-48 MUX/DEMUX
S3045
Figure 16. AC Transmitter Parallel Input Data Timing Diagram
t
PCLK
PCLK A,B,C,D
t
PICLK
PICLK
tS
tH
PIN
PIN
PINA[7:0]
PINB[7:0]
PINC[7:0]
PIND[7:0]
TIFP A,B,C,D
PARIN A,B,C,D
Table 12. AC Transmitter Parallel Data Input Timing Characteristics
Parameters
Characteristics
PCLK A, B, C, D 77.76 MHz Output Clock
PCLK A, B, C, D 77.76 MHz Output Clock duty cycle
Parallel Input Clock (PICLK) period
Min
Typ
Max Units
tPCLK
12.86
ns
40
60
60
%
ns
%
tPICLK
12.86
Parallel Input Clock (PICLK) duty cycle
40
PINA[7:0], PINB[7:0], PINC[7:0], PIND[7:0] PARIN A, B, C, D and
TIFP A, B, C, D, data setup time with respect to rising edge of PICLK
tSPIN
tHPIN
1.3
ns
PINA[7:0], PINB[7:0], PINC[7:0], PIND[7:0] PARIN A, B, C, D and
TIFP A, B, C, D, data hold time with respect to rising edge of PICLK
0.85
ns
ns
PCLK Rise and Fall Times (10%–90%)
2.5
Notes
1. Timing depicted in Figure 16 assumes PCLKA,B,C,D and PICLK are the same frequency.
2. Timing specifications are met with a 15pf load.
3. Timing specifications are measured with VDD = 3.3V at 25˚ C.
25
December 13, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
