S3042
Table 3. Output Pin Assignment and Descriptions
Pin Name
POUTN7
POUTP7
POUTN6
POUTP6
POUTN5
POUTP5
POUTN4
POUTP4
POUTN3
POUTP3
POUTN2
POUTP2
POUTN1
POUTP1
POUTN0
POUTP0
LLDP
LLDN
LLCLKP
LLCLKN
FPP
FPN
Level
LVDS
I/O
O
Pin #
14
15
16
17
18
19
20
21
28
29
30
31
32
33
34
35
99
100
90
91
37
36
SONET/SDH/ATM OC-48 1:8 RECEIVER
Description
Parallel Output. Parallel data bus, a 311 Mbps word, aligned to
the parallel output clock (POCLK). POUT<7> is the most
significant bit (corresponding to bit 1 of each PCM word, the first
bit received). POUT<0> is the least significant bit (corresponding
to bit 8 of each PCM word, the last bit received). POUT<7:0> is
updated on the falling edge of POCLK.
Diff.
LSCML
Diff.
LSCML
LVDS
O
O
O
Line Loopback Data. A retimed version of the incoming data
stream [RSD]. Enabled by LLEB.
Line Loopback Clock. A buffered version of the RSCLK input.
Enabled by LLEB.
Frame Pulse. Indicates frame boundaries in the incoming data
stream (RSD). If framing pattern detection is enabled, as
controlled by the OOF input, FP pulses high for one POCLK cycle
during the third A2 byte when a 32-bit sequence matching the
framing pattern is detected on the RSD inputs. When framing
pattern detection is disabled, FP pulses high during the third A2
byte when the incoming data stream, after byte alignment,
matches the framing pattern. FP is updated on the falling edge of
POCLK.
Parallel Output Clock. A 311MHz nominally 50% duty cycle, byte
rate output clock that is aligned to POUT<7:0> byte serial output
data. POUT<7:0> and FP are updated on the falling edge of
POCLK.
Receive Free Running 311MHz clock output. This clock is
generated by dividing the RSCLK signal by eight.
A1 A2 Frame Search Output. A High on this output pin indicates
the frame detection circuit is activated and it is searching for a new
A1 A2 byte alignment. This output will be High during the entire
period of A1 A2 frame search. Once a new alignment is found, this
signal will remain High for a minimum of one 311MHz clock period
beyond the third A2 byte before it will be set to Low.
POCLKP
POCLKN
LVDS
O
13
12
RX311MCKP
RX311MCKN
SEARCH
LVDS
LVTTL
O
O
39
38
44
6
June 24, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
