S3042
S3042 OVERVIEW
The S3042 receiver implements SONET/SDH
deserialization and frame detection functions. The
block diagram in Figure 2 shows basic operation of
the chip. This chip can be used to implement the
front end of SONET equipment, which consists pri-
marily of the serial transmit interface and the serial
receive interface. The chip includes serial-to-parallel
conversion and system timing. The system timing
circuitry consists of management of the datastream,
framing, and clock distribution throughout the front end.
SONET/SDH/ATM OC-48 1:8 RECEIVER
The sequence of operations of the S3042 is as follows:
Receiver Operations:
1. Serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 7 through 9.
Suggested Interface Devices
AMCC
AMCC
AMCC
S3040
S3045
S3041
Clock Recovery Device
OC-48 to OC-12 Mux/Demux
OC-48 Mux
Figure 2. S3042 Functional Block Diagram
SDLVPECL
1:8 SERIAL
TO PARALLEL
16
POUTP/N[7:0]
2
OOF
FRAMEN
DLEB
RSDP/N
LSDP/N
2
2
D
TIMING
FRAME GEN
BYTE
DETECT
RX311MCKP/N
POCLKP/N
FPP/N
SEARCH
KILLRXCLK
LLDP/N
2
2
M
U
X
2
D
2
2
RSCLKP/N
LSCLKP/N
M
U
X
2
LLCLKP/N
LLEB
RSTB
2
June 24, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
