S3042
RECEIVER OPERATION
The S3042 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 311 Mbyte/sec byte-serial data for-
mat. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided. Both line
and local loopback modes can be active at the same
time.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled by the Out-of-Frame
(OOF) input. Detection is enabled by a rising edge on
OOF when FRAMEN is active. It is disabled when a
framing pattern is detected. When framing pattern de-
tection is enabled, the framing pattern is used to lo-
cate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUT [7:0]) will not con-
tain valid data. The timing generator block takes the
located byte boundary and uses it to block the incom-
ing data stream into bytes for output on the parallel
output data bus (POUT[7:0]). The frame boundary is
reported on the Frame Pulse (FP) output when any
32-bit pattern matching the framing pattern is de-
tected on the incoming data stream. When framing
pattern detection is disabled, the byte boundary is
frozen to the location found when detection was pre-
viously enabled. Only framing patterns aligned to the
fixed byte boundary are indicated on the FP output.
Frame detection can be immediately disabled by
bringing FRAMEN inactive.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
µs,
even for extremely high bit error
rates.
SONET/SDH/ATM OC-48 1:8 RECEIVER
Serial-to-Parallel Converter
The Serial-to-Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version clocked by the clock recovery block. The
second is an 8-bit internal holding register, which
transfers data from the serial to parallel register on
byte boundaries as determined by the frame and
byte boundary detection block. On the falling edge of
the POCLK, the data in the holding register is trans-
ferred to an output holding register which drives
POUT[7:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is low, a loopback from the transmitter (S3041) to
the receiver (S3042) at the serial data rate can be
set up for diagnostic purposes. The differential serial
output data and clock from the transmitter (S3041)
(LSD/LSCLK) is routed to the receiver (S3042) (LSD/
LSCLK) in place of the normal data stream.
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3042, enabling line
loopback enables the LLD/LLCLK outputs. When the
line loopback enable input (LLEB) is inactive, the LLD/
LLCLK outputs are disabled. When LLEB is active,
data and clock from the primary inputs (RSD/RSCLK)
are transmitted on LLD/LLCLK, allowing a receive-to-
transmit loopback to be established at the serial data
rate. The S3042 LLD/LLCLK outputs should be con-
nected to the S3041 LLD/LLCLK inputs.
4
June 24, 1999 / Revision E
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
