SONET/SDH CLOCK RECOVERY UNIT
S3040 FUNCTIONAL DESCRIPTION
The S3040 clock recovery device performs the clock
recovery function for SONET OC-48 serial data links.
The chip extracts the clock from the serial data inputs
and provides retimed clock and data outputs. A
155.52 MHz reference clock is required for phase
locked loop start-up and proper operation under loss
of signal conditions. An integral prescaler and phase
locked loop circuit is used to multiply this reference to
the nominal bit rate.
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal with respect to REFCLKP/N
S3040B
varies by greater than the ppm specified in Table 3,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields the typical
capture time stated in Table 3 for random incoming
NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 4.
Lock Detect
The S3040 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the ppm stated
in Table 3, the PLL will be declared out of lock. The
lock detect circuit will poll the input data stream in an
attempt to reacquire lock to data. If the recovered clock
frequency is determined to be within the ppm stated in
Table 3, the PLL will be declared in lock and the lock
detect output will go active.
April 6, 2000 / Revision NC
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
