®
DEVICE
SPECIFICATION
SONET/SDH CLOCK RECOVERY UNIT
SONET/SDH CLOCK RECOVERY UNIT
BiCMOS PECL CLOCK GENERATOR
GENERAL DESCRIPTION
S3040B
S3040B
FEATURES
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Micro-power Bipolar technology
Complies with Bellcore, and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for OC-48/STM-16
(2488.32 Mbit/s) NRZ data
155.52 MHz reference frequency
Lock detect—monitors frequency
Low-jitter serial interface
+5 V supply
32 TQFP Package
The function of the S3040 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3040 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
The S3040 receives an OC-48/STM-16 scrambled
NRZ signal and recovers the clock from the data.
The chip outputs a differential bit clock and retimed
data.
The S3040 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
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8
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Network Interface
Processor
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S3045
8
8
8
8
8
S3045
S3041
MUX
8
S3042
DeMUX
OTX
ORX
S3040
DeMUX
S3041
MUX
S3042
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8
8
8
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8
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8
S3040
ORX
OTX
Network Interface
Processor
1
April 6, 2000 / Revision NC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
