SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
RECEIVER FRAMING
S3038
Figure 17 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF and remains enabled while OOF is
high. Both boundaries are recognized upon receipt
of the third A2 byte which is the first data byte to be
reported with the correct byte alignment on the out-
going data bus (POUTx[7:0]). Concurrently, the
frame pulse is set high for one POCLK cycle.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active
until the first FP pulse or until OOF goes low, which-
ever occurs last. Figure 18 shows a typical OOF
timing pattern which occurs when the S3038 is con-
nected to a down stream section terminating device.
OOF remains high for one full frame after the first FP
pulse. The frame and byte boundary detection block
is active until OOF goes low.
When interfacing with a section terminating device,
the OOF input remains high for one full frame after
the first frame pulse while the section terminating
device verifies internally that the frame and byte
alignment are correct, as shown in Figure 17. Since
at least one framing pattern has been detected since
the rising edge of OOF, boundary detection is dis-
abled when OOF is set low.
Figure 19 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and
deactivated by the first FP pulse.
Figure 17. Frame and Byte Detection
RECOVERED
CLOCK/
REFCLK
OOF
RSD
A1
A2
A2
A1
A1
A2
A2
A2
Note 1
POUTx[7:0]
A1
A1
A1
A2
A2
A2 (28H)
Valid
Data
Invalid Data
POCLK
FP
NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
Figure 18. OOF Operation Timing with PM5312
STTX or PM5355 SUNI-622
Figure 19. Alternate OOF Timing
BOUNDARY DETECTION ENABLED
BOUNDARY DETECTION ENABLED
OOF
FP
OOF
FP
27
September 16, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
