S3026
SONET/SDH/ATM CLOCK RECOVERY UNIT
Table 1. S3026 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
SERDATIP
SERDATIN
Diff.
I
I
I
2
3
Serial Data In. A clock is recovered from transitions on these
inputs.
PECL
BYPASS
SDN
TTL
16
15
Bypass Enable. Active High. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
PECL
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss
of received optical power. When SDN is inactive, the PLL will be
forced to lock to the TTLREF input and the SERDATOP/N
output will be held in the logic low state. When Signal Detect
(SDN) is active, data on the SERDATIP/N pins will be processed
normally.
TTLREF
TTL
–
I
I
7
Reference clock input used to establish the initial operating
frequency of the clock recovery PLL and also used as a standby
clock in the absence of data or when LOCKDET is inactive.
CAP1
CAP2
18
17
The loop filter capacitor and resistors are connected to these
pins. The capacitor value should be 1.0µF ±10% tolerance, X7R
dielectric. 16–50 V is recommended. The resistor values are
68Ω ±5%. See Figure 7.
LCKREFN
MODE
TTL
TTL
I
8
6
Lock to Reference. Active Low. When active, the serial clock
output will be forced to lock to the TTLREF local reference input
and the SERDATOP/N output will be held in the logic low state.
See Table 3.
I
Rate select used to select the bit rate of the device. Set High to
select 622.08 Mbit/s. Set Low to select 155.52 Mbit/s.
SERDATOP
SERDATON
Diff.
O
O
14
13
Serial Data Out signal that is the delayed version of the
incoming data stream (SERDATI) updated on the falling edge of
Serial Clock Out (SERCLKOP).
PECL
SERCLKOP
SERCLKON
Diff.
PECL
12
11
Serial Clock Out signal that is phase aligned with Serial Data
Out (SERDATOP/N). (See Figure 3.)
4
October 18, 1999 / Revision G
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
