S3026
SONET/SDH/ATM CLOCK RECOVERY UNIT
Figure 3. Clock Output to Data Transition Delay
the phase detector output into a smooth DC voltage,
and the DC voltage is input to the VCO whose fre-
quency is varied by this voltage. A block diagram is
shown in Figure 2.
SERCLKO
SERDATOP/N
OVERVIEW
t
h
t
su
The S3026 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate and
clock recovery is performed on the incoming data
stream. An external 19.44 MHz crystal oscillator is
required to minimize the PLL lock time and provide a
stable output clock source in the absence of serial
input data. Retimed data and clock are output from
the S3026.
Output Frequency
622.08 MHz
450 ps
155.52 MHz
2.5 ns
SERDATOP/N Setup Time
SERDATOP/N Hold Time
450 ps
2.5 ns
Figure 4. Input Jitter Tolerance Specification
CHARACTERISTICS
Sinusodal
Input Jitter
Amplitude
Performance
15
1.5
The S3026 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used with differential
inputs and outputs as shown in Figure 3.
(UI p-p)
0.15
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in
Figure 5. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied for each of the OC-N/STS-N rates.
f0
f2
f3
ft
f1
Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
f3
ft
(Hz) (kHz) (kHz)
12
3
10
10
30
300
300
25
250
65
30
6.5
Input Jitter Tolerance
Figure 5. Jitter Transfer Specification
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
P
slope = -20 dB/decade
Jitter
Transfer
Acceptable
Range
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
fc
Frequency
OC/STS
Level
fc
(kHz)
P
(dB)
Jitter Generation
121,2
500
130
0.1
0.1
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI when a serial data input with
less than 14 ps (OC-12) or 56 ps (OC-3) rms jitter is
presented to the serial data inputs.
31,2
1. Bellcore Specifications: TR-NWT-000253, Issue 2,
December 1991.
2. CCITT Recommendations: G.958.
October 18, 1999 / Revision G
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
