®
DEVICE
SPECIFICATION
SONET/SDH/ATM CLOCK RECOVERY UNIT
BiCMOS PECL CLOCK GENERATOR UNIT
SONET/SDH/ATM CLOCK RECOVERY
GENERAL DESCRIPTION
S3026
S3026
FEATURES
• Complies with Bellcore and ITU-T
specifications for jitter tolerance, jitter transfer
and jitter generation
• On-chip high frequency PLL with internal loop
filter for clock recovery
• Supports clock recovery for OC-12/STM-4
(S3026A) (622.08 Mbit/s) or
OC-3/STM-1 (155.52 Mbit/s) (S3026A-1)
NRZ data
• 19.44 MHz reference frequency
• Lock detect—monitors run length (S3026A only)
and frequency
• 350 mW typical power dissipation
• Low-jitter PECL interface
• Maintains downstream clock in absence of data
inputs
• Micro-power Bipolar technology
• 5V supply
• Available in a 20 TSSOP package
The function of the S3026 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3026 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
The S3026 receives either an OC-12/STM-4 or OC-3/
STM-1 scrambled NRZ signal and recovers the clock
from the data. The chip outputs a differential PECL
bit clock and retimed data. Figure 1 shows a typical
network application.
The S3026 utilizes an on-chip PLL which consists of
a phase detector, a loop filter, and a voltage con-
trolled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter converts
Figure 1. System Block Diagram
8
Transceiver
Controller
8
S3028
S3026
Fiber
Optic
Module
Fiber
Optic
Module
S3026
8
Transceiver
Controller
S3028
8
October 18, 1999 / Revision G
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
