S3024 – SONET/SDH/ATM Clock Recovery Unit
Revision G – June 5, 2002
DEVICE SPECIFICATION
Table 1. S3024 Pin Assignment and Descriptions
Pin Name
SERDATIP
SERDATIN
BYPASS
SD
Level
Diff.
LVPECL
LVTTL
LVPECL
I/O
I
I
I
Pin #
2
3
16
15
Description
Serial Data In. A clock is recovered from transitions on these inputs.
Bypass enable, active High. Used during production test to bypass the VCO in
the PLL. Tie to ground for normal operation.
Signal Detect, active High. A single-ended 10 K PECL input to be driven by
the external optical receiver module to indicate presence of received optical
power. When SD is inactive, the PLL will be forced to lock to the TTLREF
input, and the SERDATOP/N output will be held in the logic Low state. When
SD is active, data on the SERDATIP/N pins will be processed normally.
TTL Reference clock input used to establish the initial operating frequency of
the clock recovery PLL. It is also used as a standby clock in the absence of
data or when LOCKDET is inactive.
External Loop Filter Pins. The loop filter capacitor and resistors are connected
to these pins. The capacitor value should be 1.0 µF ±10% tolerance, X7R
dielectric. 50 V is recommended. The resistor values are 82
Ω
±5%.
See Figure 8.
Lock to Reference, active Low. When active, the serial clock output will be
forced to lock to the TTLREF local reference input and the SERDATOP/N out-
put will be held at the logic low state. See Table 2.
Rate select used to select the bit rate of the device. Set High to select
622.08 Mbps. Set Low to select 155.52 Mbps.
Serial Data Out signal that is the delayed version of the incoming data stream
(SERDATI). Updated on the falling edge of Serial Clock Out
(SERCLKOP).
Serial Clock Out signal that is phase aligned with Serial Data Out
(SERDATOP/N). (See Figure 3.)
Lock Detect, active High. When active, this output indicates that the PLL is
locked to the serial data inputs, and valid clock and data are present at the
serial outputs. When inactive, it indicates that the PLL is locked to the local ref-
erence clock. The lock detect will go inactive under the following conditions:
1. If SD is inactive.
2. If the VCO drifts away from the local reference clock by more than 1000 ppm.
3. If LCKREFN is active.
Lock detect will return to the active state if the serial clock is within 250 ppm of
the reference clock frequency.
Digital Ground (0 V)
Digital Power Supply (+3.3 V)
Analog Ground (0 V)
Analog Power Supply (+3.3 V)
TTLREF
LVTTL
I
7
CAP1
CAP2
–
I
18
17
LCKREFN
LVTTL
I
8
MODE
SERDATOP
SERDATON
SERCLKOP
SERCLKON
LOCKDET
LVTTL
Diff.
LVPECL
Diff.
LVPECL
LVPECL
I
O
6
14
13
12
11
5
O
O
DGND
DVCC
AGND
AVCC
GND
3.3 V
GND
3.3 V
–
–
–
–
9
10
4, 19
1, 20
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
