S3024 – SONET/SDH/ATM Clock Recovery Unit
Revision G – June 5, 2002
DEVICE SPECIFICATION
OVERVIEW
The S3024 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate, and clock
recovery is performed on the incoming data stream. A
reference clock is required to minimize the PLL lock
time and provide a stable output clock source in the
absence of serial input data. Retimed data and clock
are output from the S3024.
Figure 5. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied for each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. SONET input jitter tolerance requirements
are shown in Figure 4. The measurement condition is
the input jitter amplitude, which causes an equivalent
of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Jitter Generation
The jitter generation of the serial clock and serial data
outputs shall not exceed the value specified in Table 6
when a serial data input with less than 14 ps (OC-12)
or 56 ps (OC-3) rms jitter is presented to the serial
data inputs.
JITTER CHARACTERISTICS
Performance
The S3024 PLL complies with the jitter specifications
proposed for SONET/SDH equipment as defined by
the T1X1.6/91-022 document when used with differen-
tial inputs and outputs as shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of jit-
ter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in
Figure 3. Clock Output to Data Transition Delay
SERCLKO
SERDATOP/N
t
h
t
su
Output Frequency
622.08 MHz
SERDATOP/N Setup Time
SERDATOP/N Hold Time
500 ps
500 ps
155.52 MHz
2.5 ns
2.5 ns
3