Part Number S3024
Revision G – June 5, 2002
S3024
SONET/SDH/ATM Clock Recovery Unit
FEATURES
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Complies with Bellcore and ITU-T specifications
for jitter tolerance, jitter transfer and jitter
generation
On-chip high-frequency PLL with internal loop
filter for clock recovery
Supports clock recovery for OC-12/STM-4
(622.08 Mbps) or OC-3/STM-1 (155.52 Mbps)
NRZ data
19.44 MHz reference frequency
Lock detect—monitors frequency
264 mW typical power dissipation
Low-jitter LVPECL interface
Maintains downstream clock in absence of
data inputs
3.3 V supply
Available in a 20-pin TSSOP package
Active High LVPECL Signal Detect
DEVICE SPECIFICATION
GENERAL DESCRIPTION
The function of the S3024 clock recovery unit is to
derive high-speed timing signals for SONET/SDH-
based equipment. The S3024 is implemented using
AMCC's proven Phase Lock Loop (PLL) technology.
The S3024 receives either an OC-12/STM-4 or OC-3/
STM-1 scrambled NRZ signal and recovers the clock
from the data. The chip outputs a differential LVPECL
bit clock and retimed data. Figure 1 shows a typical
network application.
The S3024 utilizes an on-chip PLL, which consists of a
phase detector, a loop filter, and a Voltage Controlled
Oscillator (VCO). The phase detector compares the
phase relationship between the VCO output and the
serial data input. A loop filter converts the phase
detector output into a smooth DC voltage, and the DC
voltage is input to the VCO, whose frequency is varied
by this voltage. A block diagram is shown in Figure 2.
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Figure 1. System Block Diagram
8
Transceiver
Controller
8
S3033
S3024
Fiber
Optic
Module
Fiber
Optic
Module
S3024
Transceiver
8
Controller
S3033
8
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
