SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
S3019
Table 5. S3019 Transmitter Pin Assignment and Descriptions (Active High unless otherwise stated.)
Pin Name
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
PICLK
Level
LVTTL
I/O
I
Pin #
72
71
70
69
68
67
66
65
74
Description
Parallel Data Input, a 77.76 Mbps or 19.44 Mbps word, aligned
to the PICLK parallel input clock. PIN[7] is the most significant
bit (corresponding to bit 1 of each PCM word, the first bit
transmitted). PIN[0] is the least significant bit (corresponding to
bit 8 of each PCM word, the last bit transmitted). PIN[7:0] is
sampled on the rising edge of PICLK.
LVTTL
I
Parallel input clock, a 77.76 or 19.44 MHz, nominally 50% duty
cycle input clock, to which PIN[7:0] is aligned. PICLK is used to
transfer the data on the PIN inputs into a holding register in the
parallel-to-serial converter. The rising edge of PICLK samples
PIN[7:0]. After a master reset, two rising edges of PICLK are
required to fully initialize the internal datapath.
Loop Filter Capacitor. The external loop filter capacitor and
resistors are connected to these pins. The capacitor value
should be 0.01µF ±10% tolerance, X7'R dielectric. 50 volt is
recommended (16 volt is acceptable).
Transmit Serial Data. Differential LVPECL serial data stream
signals, normally connected to an optical transmitter module.
Transmit Serial Clock. Clock that can be used to retime the
TSD signal. This clock will be 622.08 MHz or 155.52 MHz,
depending on the operating mode.
Parallel Clock. A Parallel Clock is generated by dividing the
internal bit clock by eight. It is normally used to coordinate
byte-wide transfers between upstream logic and the S3019
device.
38 MHZ Clock Output. A 38.88 MHz clock which can be used
as a stable clock source by the controller device. This clock is
divided down from the transmit serial clock and operates at
38.88 MHz for all operating modes.
Parity Input. Odd parity input for the 8-bit PIN[7:0] data bus.
CAP1
CAP2
Analog
I
12
11
TSDP
TSDN
TSCLKP
TSCLKN
PCLK
Diff.
LVPECL
Diff.
LVPECL
LVTTL
O
21
22
25
24
76
O
O
38MHZCLK
LVTTL
O
1
PARIN
LVTTL
I
73
PARERR
LVTTL
O
77
Parity Error. Indicates to the controller that a parity error has
been detected on the PIN[7:0] data bus for the previous byte of
data.
51 MHz Clock Output. A 51.84 MHz clock which can be used
as a stable clock source by the controller device. This clock is
divided down from the clock synthesis PLL serial clock and
operates at 51 MHz for all operating modes.
19 MHz Clock Output. A 19.44 MHz clock output which is
intended to be connected to the fiber optic module backup
reference clock if a clock and data recovery circuit is used
inside the module. This will maintain downstream clocking
under loss of signal conditions. This clock is divided down from
the clock synthesis PLL serial clock and operates at 19.44 MHz
for all operating modes.
51MHZCLK
LVTTL
O
3
19MHZCLK
LVTTL
O
80
April 12, 2000 / Revision F
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
