S3019
Clock Recovery
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
Lock Detect
The S3019 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the received
serial data fails the run length or frequency test, the
PLL will be forced to lock to the local reference clock.
This will maintain the correct frequency of the POCLK
output under loss of signal or loss of lock conditions. If
the serial data inputs have a run length greater than
80-bit times with no transitions, the PLL will be de-
clared out of lock. In addition, if the recovered clock
frequency deviates from the local reference clock fre-
quency by more than the specified ppm, the PLL will
also be declared out of lock. The lock detect circuit will
poll the input data stream in an attempt to reacquire
lock to data. If the recovered clock frequency is deter-
mined to be within the specified ppm and the run
length check indicates valid data, the PLL will be de-
clared in lock and the lock detect output will go active.
See Table 9.
Backup Reference Generator
The backup reference generator seen in Figure 4
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock REFCLKP/N.
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected and
OOF is no longer set High. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming
data stream (RSD or looped transmitter data). The
timing generator block takes the located byte bound-
ary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUTP/N[7:0]). The frame boundary is reported on
the Frame Pulse (FP) output when any 48-bit pattern
matching the framing pattern is detected on the in-
coming data stream. When framing pattern detection
is disabled, the byte boundary is frozen to the loca-
tion found when detection was previously enabled.
Only framing patterns aligned to the fixed byte
boundary are indicated on the FP output.
April 12, 2000 / Revision F
Clock recovery, as shown in the block diagram in
Figure 4, generates a clock that is at the same fre-
quency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a PLL so that it samples
the data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by greater than the
value specified in Table 9 with respect to
REFCLKP/N, the PLL will be declared out of lock,
and the PLL will lock to the reference clock. The
assertion of LOS will also cause an out of lock condi-
tion.
The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal. This transfer function yields the
typical capture time stated in Table 9 for random
incoming NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 5.
Figure 5. Clock Recovery Jitter Tolerance
Jitter
15
Amplitude
(Ul p-p)
1.5
Minimum proposed
tolerance
(TA-NWT-000253)
OC-3
OC-12
0.15
30
300
6.5k 25k 65k
Jitter Frequency (Hz)
250k
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
