S3019
Reference Loop Timing
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
The S3019 has been designed (BYPASS mode) for
operation with clock recovery devices that provide
continuous serial clock for seamless downstream
clocking in the event of optical signal loss. For op-
eration with an optical transceiver that provides the
“squelched clock” behavior as described above, the
S3019 can be operated in the “squelched clock
mode” by activating the SQUELCH pin.
In this condition, the receive serial clock RSCLKP/N
is used for all receiver timing when the SDPECL/
SDTTL inputs are in the active state. When the
SDPECL/SDTTL inputs are place in the inactive
state (usually by the deassertion of LOCKDET or
signal detect from the optical transceiver/clock re-
covery unit) the transmitter serial clock will be used
to maintain timing in the receiver section. This will
allow the POCLK to continue to run and the parallel
outputs to flush out the last received characters and
the assume the all zero state imposed at the serial
data input.
It is important to note that in this mode there will be a
random 1.6 nsec shortening or lengthening of the
POCLK cycle, resulting in an apparent phase shift in
the POCLK at the deassertion of the SD condition.
Another similar phase shift will occur when the SD
condition is reasserted.
In the normal operating mode with both BYPASS
and SQUELCH inputs inactive, there will be no
phase discontinuities at the POCLK output during
signal loss or reacquisition (assuming operation with
continuous clocking from the CRU device such as
the AMCC S3026 or S3027).
In reference loop timing mode, the clock synthesizer
PLL is still used as the clock source for the transmit
section. However, the parallel receive clock is used
as the reference clock for the clock synthesizer PLL.
The MODE[1:0] inputs must be in the 1,1 state for
STS-12 operation or 0,NC for STS-3 operation.
Forward Clocking
For both 77.78 MHz and 38.88 MHz reference op-
eration, the S3019 operates in the forward clocking
mode. The PLL locks the PCLK output of the trans-
mitter section to the REFCLK with a fixed and
repeatable phase relation. This allows the transmit-
ter data source to also be the timing source for the
serial clock synthesis.
The rising edge of PCLK is locked to the rising edge
of REFCLKP, with a maximum delay of 8 to 10 nsec
due to the PCLK TTL output driver.
For operation at 19.44 MHz and 51.84 MHz refer-
ences, separate timing paths are use for PLL control
and PCLK generation, and forward clocking is not
recommended.
“Squelched Clock” Operation
Some integrated optical receiver/clock recovery
modules force their recovered serial receive clock
output to the logic zero state if the optical signal is
removed or reduced below a fixed threshold. This
condition is accompanied by the expected
deassertion of the signal detect output.
8
April 12, 2000 / Revision F
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
