S3014
Performance Specifications
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Parameter
Nominal VCO
Center Frequency
Clock Synthesis Output
Jitter
OC-3/STS-3
OC-12/STS-12
1
Clock Recovery Output
Jitter
Reference Clock
Frequency Tolerance
2,3
Clock Synthesis
Clock Recovery
OC-3/STS-3
OC-12/STS-12
Capture Range
Lock Range
Clock Output
Duty Cycle
Acquisition Lock Time
3
OC-3/STS-3
OC-12/STS-12
Reference Clock
Input Duty Cycle
Reference Clock Rise &
Fall Times
ECL Output Rise & Fall
Times
Min
Typ
622.08
Max
Units
MHz
Condition
Given REFCLK = SERCLK
÷
4,
12 or SERCLK
÷
32 per SEL
<2:0> settings
In CSU mode, given :
.005
.01
64
.03
48
.01
UI(rms)
ps (rms)
UI(rms)
ps (rms)
UI(rms)
• 56ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
• 14.1 ps rms jitter on REFCLK
in 12 KHz to 1 MHz band
rms jitter, in lock
Required to meet SONET output
frequency specification
.015
-20
-100
20
100
ppm
ppm
±200
+8,-12
45
55
64
16
30
70
2.0
850
ppm
%
%
µsec
% of
period
ns
ps
With respect to fixed reference
frequency
Minimum transition density of
20%
With device already powered up
and valid REFCLK.
10% to 90% of amplitude
10% to 90%, 50Ω to -2V
equivalent load, 5 pf cap
1. These specs can be achieved with either a 51.84 MHz or a 155.52 MHz Reference Clock.
2. Noise on REFCLK should be less than 14.1 ps rms in a jitter frequency band from 12 KHz to 1 MHz.
3. Specifications based on design values. Not tested.
Table 1. Mode Select
SEL2 SEL1 SEL0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SERCLKO
622.08 MHz
622.08 MHz
622.08 MHz
622.08 MHz
155.52 MHz
155.52 MHz
REFCKOUT
51.84 MHz
19.44 MHz
19.44 MHz
—
51.84 MHz
19.44 MHz
REFCKIN
51.84 MHz
19.44 MHz
19.44 MHz
155.52 MHz
51.84 MHz
19.44 MHz
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
