S3014
SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Pin Assignment and Descriptions (Continued)
Pin Name
SERDATOP
SERDATON
SERCLKOP
SERCLKON
Level
Diff.
ECL
Diff.
ECL
I/O
O
Pin #
20
21
15
14
Description
Serial data out signal. In the Clock Recovery mode, this signal is
the delayed version of the incoming data stream (SERDATI)
updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial clock out signal that is phase aligned with Serial Data Out
(SERDATO) when Lock Detect (LOCKDET) is high. When Lock
Detect is low, the signal is synchronous with Reference Clock
(REFCKINP/N).
Single-ended TTL reference clock output. See Table 1.
Analog power (-5.2V)
Analog ground (0V)
O
REFCKOUT
AVEE
AGND
TTL
-5.2V
GND
O
–
–
31
2, 5, 7,
38, 44
1, 3, 8,
37, 42
GND
GND
–
9, 16, 17, Ground
19, 22,
27, 29,
30, 35
10, 13,
25, 34
18, 28
12
-5.2V
+5V
No Connection
-5.2V
+5V
NC
-5.2V
+5V
–
–
–
–
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
