SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT
Pin Assignment and Descriptions
S3014
Pin Name
REFCKINP
REFCKINN
SERDATIP
SERDATIN
TSTCLKEN
SEL2
SEL1
SEL0
RST
Level
Diff.
ECL
Diff.
ECL
TTL
TTL
I/O
I
Pin #
41
43
4
6
36
26
24
23
33
Description
Reference clock. Input used as the reference for the internal bit
clock in frequency synthesis mode. Used as standby clock in the
absence of data or during reset in clock recovery mode.
Serial data in. When the S3014 is used in the Clock Recovery
mode, clock is recovered from the transitions on these inputs.
Test clock enable, active high. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
Mode select, used to select output and input frequencies. Refer
to Table 1 for explanation.
Reset, active low. Initializes the device to a known state and
forces the PLL to acquire to the reference clock. RST, when held
low, also forces the REFCKOUT and LOCKDET outputs to the
Hi-Z state. A reset of at least 16 ms should be applied at power-
up and whenever it is necessary to reacquire to the reference
clock. The S3014 will also reacquire to the reference clock if the
serial data is held quiescent (constant ones or constant zeros)
for at least 16 ms.
Loss of signal, active low. A single-ended 10K ECL input to be
driven by the external optical receiver module to indicate a loss
of received optical power. When LOS is low, the data on the
Serial Data In (SERDATIP/N) pins will be internally forced to a
constant zero, LOCKDET forced low, and the PLL forced to lock
to the REFCKINP/N inputs. This signal must be used to assure
correct automatic reacquisition to serial data following an
interruption and subsequent reconnection of the optical path.
This will assure that the PLL does not "wander" out of
reacquisition range by tracking the random phase/frequency
content of the optical detector's noise floor while monitoring
"dark" fiber. When LOS is high, data on the SERDATIP/N pins
will be processed normally.
Loop filter capacitor, connected to these pins. The capacitor
value should be 0.1 µf ±10% tolerance, X7R dielectric ceramic
chip capacitor. 50V is recommended.
Lock detect, active high. Clock recovery indicator. Set high when
the internal clock recovery has locked onto the incoming
datastream. LOCKDET is an asynchronous output. This output
is deasserted when there is no incoming serial data input; in
which case the PLL locks to the reference clock.
I
I
I
TTL
I
LOS
ECL
I
32
CAP1, CAP2
–
I
39
40
11
LOCKDET
TTL
O
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
