SERIAL BACKPLANE RETIMER DEVICE
S2092
Table 3. Pin Assignment and Descriptions
Pin Name
Level
I/O Pin#
Description
SERDATIP
SERDATIN
Diff.
CML
3
2
Serial Data In. Clock is recovered from the transitions on these inputs.
Internally biased and terminated. (See Figure 8.)
I
Active High. Used to bypass the PLL. It allows transmission of the data
input without clock recovery.
BYPASS
LVTTL
I
I
46
45
Signal Detect. Active Low. A single-ended 10K PECL input to be driven
by the external optical receiver module to indicate a loss of received
optical power. When SDN is inactive, the data on the Serial Data In
(SERDATIP/N) pins will be internally forced to a constant zero and the
PLL will be forced to lock to the REFCLK input. When SDN is active,
data on the SERDATIP/N pins will be processed normally.
Single
Ended
LVPECL
SDN
Reference Clock. 155.52 to 166.63 or 19.44 to 20.83 MHz (see Tables
1 and 2 for additional reference clock frequencies) input used to
establish the initial operating frequency of the clock recovery PLL and
also used as a standby clock in the absence of data, during reset, or
when SDN is inactive. Internally biased.
Internally
Biased
Diff.
REFCLKP
REFCLKN
6
7
I
LVPECL
CAP1
CAP2
40 Loop Filter Capacitor. The external loop filter capacitor and resistors
39 are connected to these pins. (See Figure 11.)
I
I
Lock to Reference. Active Low. When active, the serial data output will
LCKREFN
LVTTL
17
be invalid.
Test input signal used for production test. Leave open (no DC
connection) for normal operation.
TESTCLK
REFSEL
RST
LVTTL
LVTTL
LVTTL
I
I
I
15
18 Selects the reference frequency (See Tables 1 and 2.)
Active High. Resets lock detect circuit and VCO divide-by-N circuit for
production test.
16
Test Enable. Active High. Bypasses the VCO for production test. Tie
Low for normal operation.
TESTEN
LVTTL
I
47
SERDATOP
SERDATON
Diff.
CML
28 Serial Data Out. This signal is the delayed version of the incoming data
27 stream (SERDATI).
O
Lock Detect. Clock recovery indicator. Set High when the internal clock
10 recovery has locked onto the incoming data stream. LOCKDET is an
asynchronous output.
LOCKDET
LVTTL
O
TESTOUT1
TESTOUT2
TESTMODE1
TESTMODE2
O
O
I
23 Test Output. Leave open (no DC connection) for normal operation.
33 Test Output. Leave open (no DC connection) for normal operation.
19 Test Mode Control. Keep High for normal operation.
LVTTL
LVTTL
I
20 Test Mode Control. Keep High for normal operation.
July 10, 2000 / Revision A
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
