SERIAL BACKPLANE RETIMER DEVICE
S2092 FUNCTIONAL DESCRIPTION
S2092
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by a value greater than
that stated in Table 7 with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The S2092 retimer device performs clock recovery
function from 2.488 Gbps to 2.67 Gbps serial data
links. The chip extracts the clock from the serial data
inputs and provides retimed data outputs. A 155.52
to 166.63 or 19.44 to 20.83 MHz reference clock is
required (REFCLK frequency is dependent on which
FEC capability is required. See Table 2 for the
number of bytes per 255 byte block to set the proper
reference frequency.) for phase lock loop start up
and proper operation under loss of signal conditions.
An integral prescaler and phase lock loop circuit is
used to multiply this reference to the nominal bit rate.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density in a received data signal.
Lock Detect
The S2092 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than that stated in
Table 7, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within that range stated in
Table 7, the PLL will be declared in lock and the lock
detect output will go active. The assertion of SDN will
also cause an out of lock condition.
Data Retiming
Data retiming, as shown in the block diagram in Fig-
ure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Table 1. Reference Frequency Select
REFSEL
Reference Frequency
19.44 to 20.83 MHz
155.52 to 166.63 MHz
0
1
Table 2. FEC Modes
Reference Frequency for Data Rates with FEC Capability of X bytes per 255–Byte Block
REFSEL
X = 0
X = 3
X = 4
X = 5
X = 6
X = 7
X = 8
0
1
19.44 MHz
19.99 MHz 20.15 MHz 20.31 MHz 20.48 MHz 20.65 MHz 20.83 MHz
155.52 MHz 159.91MHz 161.21 MHz 162.53 MHz 163.87 MHz 165.26 MHz 166.63 MHz
July 10, 2000 / Revision A
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
