S2092
SERIAL BACKPLANE RETIMER DEVICE
Suggested Interface Devices
S2092 OVERVIEW
AMCC
AMCC
AMCC
AMCC
S2018
S3083
S3063
S3044
17 x 17 3.2 Gbps Crosspoint Switch
OC-48 16:1Transmitter
The S2092 supports clock recovery from 2.488 Gbps
to 2.67 Gbps data rate. Differential serial data is input
to the chip at the specified rate, and clock recovery is
performed on the incoming data stream. An external
oscillator is required to minimize the PLL lock time.
Retimed data is output from the S2092.
OC-48 Differential 16:1 Transmitter
OC-48 1:16 Receiver
Multi-Rate SONET/SDH/ATM
Transceiver
AMCC
AMCC
S3057
S3067
Multi-Rate SONET/SDH/ATM
Transceiver w/FEC
Mulit-Rate Clock and Data
Recovery Unit
AMCC
AMCC
S3056
S3052
Mulit-Rate Performance Monitor
Figure 2. S2092 Functional Block Diagram
2
LOOP
FILTER
VCO
CAP 1,2
TESTOUT 1
TESTOUT 2
REFCLKP/N
TESTCLK
CLOCK
DIVIDER
REFSEL
TESTEN
LOCK
DETECTOR
LOCKDET
LCKREFN
RST
PHASE DETECTOR
SERDATOP/N
SDN
SERDATIP/N
BYPASS
July 10, 2000 / Revision A
2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
