DUAL GIGABIT ETHERNET TRANSCEIVER
S2068
Table 14. Transmitter Timing
Parameters
SDR, TSDF
Description
Min
Max Units
Conditions
20% - 80%, tested on sample basis.
4.5 kΩ to ground.
T
Serial Data Rise and Fall
300
192
ps
ps
Peak-to-peak, measured on sample
basis. Measured with ±K28.5 or 27-1
pattern at 1.25 GHz.
Serial Data Output total jitter
(p-p)
TJ
Peak-to-peak, tested on a sample
basis. Measured with ±K28.5 pattern
at 1.25 GHz.
Serial Data Output
deterministic jitter (p-p)
TDJ
80
ps
Figure 12. TCLKO Timing
REFCLK
T3
TCLKO
Table 15. S2068 Transmitter (TCLKO Timing)
Parameters
Description
Min
2
Max
7.5
Units
ns
Conditions
T3
TCLKO w.r.t. REFCLK
TCLKO Duty Cycle
40%
60%
%
Note: Measurements are made at 1.4V level of clocks.
17
October 13, 2000 / Revision D
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
