®
DEVICE
SPECIFICATION
S2064 QUAD SERIAL BACKPLANE DEVICE
QUAD SERIAL BACKPLANE DEVICE
GENERAL DESCRIPTION
S2064
S2064
FEATURES
• Broad operating rate range (0.7 - 1.3 GHz)
– 1062 MHz (Fibre Channel)
– 1250 MHz (Gigabit Ethernet) line rates
– 1/2 Rate Operation
• Quad Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data
recovery
• Internally series terminated TTL outputs
• On-chip 8B/10B line encoding and decoding for
four separate parallel 8-bit channels
• 32-bit parallel TTL interface
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.3 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
The S2064 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides four
separate transceivers which can be operated indi-
vidually or locked together for an aggregate data
capacity of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates approximately 2.3 watts.
Figure 1 shows the S2064 and S2066 in a Gigabit
Ethernet application. Figure 2 combines the
S2064 with a crosspoint switch to demonstrate a
serial backplane application. Figure 3 is the input/
output diagram. Figures 4 and 5 show the transmit
and receive block diagrams, respectively.
APPLICATIONS
•
•
•
•
•
•
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE
SERIAL BP DRIVER
MAC
(ASIC)
QUAD
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2066
MAC
(ASIC)
S2064
MAC
(ASIC)
October 13, 2000 / Revision G
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
