S2064 QUAD SERIAL BACKPLANE DEVICE
Table 2. K Character Generation (SOFx = 0)
K
Character
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
Current RD+
DIN[7:0]
000 11100
001 11100
010 11100
011 11100
100 11100
101 11100
110 11100
111 11100
111 10111
111 11011
111 11101
111 11110
KGEN
abcdei fghj
1
1
1
1
1
1
1
1
1
1
1
1
110000 1011
110000 0110
110000 1010
110000 1100
110000 1101
110000 0101
110000 1001
110000 0111
000101 0111
001001 0111
010001 0111
100001 0111
abcdei fghj
001111 0100
001111 1001
001111 0101
001111 0011
001111 0010
001111 1010
001111 0110
001111 1000
111010 1000
110110 1000
101110 1000
011110 1000
Current RD-
Comments
S2064
Sync Character
Table 3. Data to 8B/10B Alphabetic Representation
Data Byte
DIN[0:9] or DOUT[0:9]
8B/10B Alphanumeric Representation
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 4.
When operating in the CHANNEL LOCK mode, the
user must insure that the path length of the four high
speed serial data signals are matched to within 50
serial bit times of delay. Failure to meet this require-
ment may result in bit errors in the received data or
in byte misalignment. In addition to path length in-
duced timing skew, the S2064 can tolerate up to
±3
ns of phase drift between channels after deskewing
the outputs.
Test Functions
The S2064 can be configured for factory test to aid
in functional testing of the device. When in the test
mode, the internal transmit and receive voltage-con-
trolled oscillator (VCO) is bypassed and the refer-
ence clock substituted. This allows full functional
testing of the digital portion of the chip or bypassing
the internal synthesized clock with an external clock
source. (See Other Operating Modes section.)
Table 4. Operating Rates
RATE
0
0
1
1
CLKSEL
0
1
0
1
REFCLK
Frequency
SDR/10
SDR/20
SDR/10
SDR/20
Serial Output
Rate
0.77–1.3 GHz
0.77–1.3 GHz
0.39-0.65 GHz
0.39-0.65 GHz
TCLKO
Frequency
SDR/10
SDR/10
SDR/10
SDR/10
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. The DIN FIFO is
automatically reset upon power up immediately after
the DIN PLL obtains steady state timing at this point,
then the user must initialize by asserting the RESET
signal. The TCLKO will operate normally regardless
of the state of RESET.
Note: SDR = Serial Data Rate.
Serial Data Outputs
The S2064 provides LVPECL level serial outputs. Each
high speed output should be provided with a resistor to
VSS (Gnd) near the device. A value of 4.5 KΩ provides
optimal performance with minimum impact on power
dissipation. The resistance may be as low as 450
Ω,
but this will dissipate additional power with no substan-
tive performance improvement. Outputs are designed
to perform optimally when AC-coupled.
October 13, 2000 / Revision G
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
