S2062
Table 3. K Character Generation (SOFx = 0)
K
Character
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
Current RD+
DIN[7:0]
000
001
010
011
100
101
110
111
111
111
111
111
11100
11100
11100
11100
11100
11100
11100
11100
10111
11011
11101
11110
KGEN
abcdei fghj
1
1
1
1
1
1
1
1
1
1
1
1
110000
110000
110000
110000
110000
110000
110000
110000
000101
001001
010001
100001
1011
0110
1010
1100
1101
0101
1001
0111
0111
0111
0111
0111
DUAL SERIAL BACKPLANE DEVICE
Current RD-
Comments
abcdei fghj
001111
001111
001111
001111
001111
001111
001111
001111
111010
110110
101110
011110
0100
1001
0101
0011
0010
1010
0110
1000
1000
1000
1000
1000
Sync Character
Table 4. Data to 8B/10B Alphabetic Representation
Data Byte
DIN[0:9] or DOUT[0:9]
8B/10B Alphanumeric Representation
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 5.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
Table 5. Operating Rates
RATE
0
CLKSEL
0
1
0
1
REFCLK
Frequency
SDR/10
SDR/20
SDR/10
SDR/20
Serial Output
Rate
0.77–1.3 GHz
0.77–1.3 GHz
0.39-0.65 GHz
0.39-0.65 GHz
TCLKO
Frequency
SDR/10
SDR/10
SDR/10
SDR/10
Serial Data Outputs
The S2062 provides LVPECL level serial outputs. Each
high speed output should be provided with a resistor to
VSS (Gnd) near the device. A value of 4.5 KΩ provides
optimal performance with minimum impact on power
dissipation. The resistance may be as low as 450
Ω,
but this will dissipate additional power with no sub-
stantive performance improvement. Outputs are de-
signed to perform optimally when AC-coupled.
0
1
1
Note: SDR = Serial Data Rate.
8
October 13, 2000 / Revision C
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
