DUAL SERIAL BACKPLANE DEVICE
8B/10B Decoding
S2062
OTHER OPERATING MODES
Operating Frequency Range
After serial to parallel conversion, the S2062 pro-
vides 8B/10B decoding of the data. The received 10-
bit codeword is decoded to recover the original 8-bit
data. The decoder also checks for errors and flags,
either invalid codeword errors or running disparity
errors by assertion of the ERRx signal. Error type is
determined by examining the EOF output in accor-
dance with Table 7. When more than one reportable
condition occurs simultaneously, reporting is in ac-
cordance with the rank assigned by Table 7.
The S2062 is designed to operate at serial baud
rates of 0.77 GHz to 1.3 GHz (616 Mbps to 1040
Mbps user data rate). The part is specified at Fibre
Channel (1062 MHz) and Gigabit Ethernet (1.25
GHz) serial baud rates, but will operate satisfactorily
at any rate in this range.
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver, as shown in Figure 8. This provides the
ability to perform system diagnostics and off-line
testing of the interface to verify the integrity of the
serial channel before enabling the transmission me-
dium. Loopback mode can be simultaneously en-
abled for both channels using the loopback-enable
input, LPEN. Note that the high speed outputs are
disabled during loopback operation.
Data Output
Data is output on the DOUT[0:7] outputs. K-characters
are flagged using the KFLAG signal. The EOF (with
KFLAG) is used to indicate the reception of a valid
K28.5 character. Invalid codewords and decoding er-
rors are indicated on the ERR output. KFLAG, EOF,
and ERR are buffered with the data in the FIFO to
insure that all outputs are synchronized at the S2062
outputs. Errors are reported independently for each
channel in TCLK or REFCLK mode operation.
TEST MODES
The S2062 TTL outputs are optimized to drive 65Ω
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
The RESET pin is used to initialize the Transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization).
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 8. When CMODE is HIGH, a complementary
TTL clock at the data rate is provided on the RCxP/N
outputs. Data should be clocked on the rising edge
of RCxP. When CMODE is LOW, a complementary
TTL clock at 1/2 the data rate is provided. Data
should be latched on the rising edge of RCxP and
the rising edge of RCxN.
Figure 8. S2062 Diagnostic Loopback Operation
output
disabled
CSU
CRU
In Fibre Channel and Gigabit Ethernet applications,
multiple consecutive K28.5 characters cannot be
generated. However, for serial backplane applica-
tions this can occur. The S2062 must be able to
operate properly when multiple K28.5 characters are
received. After the first K28.5 is detected and
aligned, the RCxP/N clock will operate without
glitches or loss of cycles.
Table 8. Output Clock Mode
Mode
CMODE
RCx P/N Freq
VCO/20
Half Clock Mode
Full Clock Mode
0
1
VCO/10
October 13, 2000 / Revision C
11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
