S2062
DUAL SERIAL BACKPLANE DEVICE
Table 9. Transmitter Input Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
DINA7
TTL
I
P12
T14
R12
P11
T13
R11
T12
P10
Transmit Data for Channel A. Parallel data on this bus is
clocked in on the rising edge of TCLKA or REFCLK.
DINA6
DINA5
DINA4
DINA3
DINA2
DINA1
DINA0
SOFA
TTL
TTL
TTL
I
I
I
T15
R13
R10
Start of Frame A. SOFA High causes the K28.5 character of
appropriate parity to be transmitted on channel A outputs.
KGENA
TCLKA
K-Character Generation. KGENA High causes the data on
DINA[0:7] to be encoded into a K-Character.
Transmit Data Clock A. When TMODE is High, this signal is
used to clock Data on DINA[0:7], KGENA, and SOFA into the
S2062. When TMODE is Low, TCLKA is ignored.
DINB7
DINB6
DINB5
DINB4
DINB3
DINB2
DINB1
DINB0
TTL
I
M16
M15
M14
N16
N15
N14
P16
P15
Transmit Data for Channel B. Parallel data on this bus is clocked
in on the rising edge of TCLKB or REFCLK.
SOFB
TTL
TTL
TTL
I
I
I
L15
L14
R16
Start of Frame B. SOFB High causes the K28.5 character of
appropriate parity to be transmitted on channel B outputs.
KGENB
TCLKB
K-Character Generation. KGENB High causes the data on
DINB[0:7] to be encoded into a K-Character.
Transmit Data Clock B. When TMODE is High, this signal is
used to clock Data on DINB[0:7], KGENB, and SOFB into the
S2062. When TMODE is Low, TCLKB is ignored.
Table 10. Transmitter Output Signals
Pin Name
Level
I/O
Pin #
Description
TXAP
TXAN
Diff.
LVPECL
O
D16
E15
High speed serial outputs for Channel A.
TXBP
TXBN
Diff.
LVPECL
O
O
G15
G16
High speed serial outputs for Channel B.
TCLKO
TTL
K14
TTL Output Clock at the Parallel data rate. This clock is provided
for use by up-stream circuitry.
October 13, 2000 / Revision C
12
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
